Simulation Results

Simulation Results: rv_dm/use_dmi_interface

17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.01 %

code
74.37 %

assert
96.59 %

func
93.08 %

block
90.02 %

line
89.78 %

branch
72.94 %

toggle
72.25 %

FSM
62.50 %

Validation stages

V1		92.59%
V2		69.57%
V2S		100.00%
V3		100.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	32.000s	1729.939us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	31.000s	332.796us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	30.000s	190.368us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	30.000s	7002.472us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	30.000s	548.719us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	31.000s	3951.360us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	30.000s	2689.486us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	96.000s	53240.330us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	75.000s	82671.738us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	33.000s	519.333us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	31.000s	195.364us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	248.831us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	30.000s	166.562us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	31.000s	465.952us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	36.000s	731.819us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	29.000s	192.144us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	33.000s	486.709us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	33.000s	519.333us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	30.000s	269.229us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	31.000s	843.968us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	248.831us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	31.000s	43.385us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	30.000s	126.131us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	30.000s	78.692us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	53.000s	4124.843us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	56.000s	6132.850us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	31.000s	114.885us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	56.000s	6132.850us	1	1	100.00
	rv_dm_csr_rw	30.000s	78.692us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	30.000s	126.606us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	31.000s	130.571us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	32.000s	1729.939us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	32.000s	282.615us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	32.000s	629.184us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	32.000s	127.573us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	31.000s	1202.220us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	35.000s	3239.578us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	32.000s	574.418us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	30.000s	52.391us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	34.000s	4856.579us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	29.000s	120.654us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	32.000s	920.071us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	33.000s	866.974us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	32.000s	162.780us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	45.000s	9874.919us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	48.000s	2048.738us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	31.000s	77.177us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	29.000s	242.619us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	29.000s	47.309us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	32.000s	137.934us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	32.000s	137.934us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	56.000s	6132.850us	1	1	100.00
	rv_dm_csr_hw_reset	30.000s	126.131us	1	1	100.00
	rv_dm_csr_rw	30.000s	78.692us	1	1	100.00
	rv_dm_same_csr_outstanding	32.000s	375.737us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	56.000s	6132.850us	1	1	100.00
	rv_dm_csr_hw_reset	30.000s	126.131us	1	1	100.00
	rv_dm_csr_rw	30.000s	78.692us	1	1	100.00
	rv_dm_same_csr_outstanding	32.000s	375.737us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	32.000s	1316.935us	1	1	100.00
	rv_dm_tl_intg_err	42.000s	1868.772us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	42.000s	1868.772us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	920.071us	1	1	100.00
	rv_dm_debug_disabled	31.000s	139.082us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	920.071us	1	1	100.00
	rv_dm_debug_disabled	31.000s	139.082us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	32.000s	1729.939us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	32.000s	610.037us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	311.785us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	311.785us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	32.000s	610.037us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	rv_dm_stress_all_with_rand_reset	61.000s	3619.279us	1	1	100.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	97.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	17839575429869963573855909769281001087099049053370516927680898118937563396144	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23816
	rv_dm_autoincr_sba_tl_access	56910587335038687054265594588266878805752284647547544367119257452715773726249	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23865
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	41959092999562350706643664738922482415280952893075067398836519648853797700026	107	UVM_INFO @ 574418494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	2738114077114825491159847882484110450823971261473108082940267137263634539650	107	UVM_INFO @ 52390640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	838178092149728276190215570059125195251015856025961921135377993196349493196	87	UVM_INFO @ 166562455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	97746114456615903336990759246821318667161162771658666894468342479471455891856	89	UVM_INFO @ 242619301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	85911326277375068754470035411248897477328421469942906970748379894803444625270	87	UVM_INFO @ 162779856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	45441822961048821001675006421377074155292327862865262352895422636195034410478	87	UVM_INFO @ 120653960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23861) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	71236609425349160802940662975294785628822486473827767159243307655302683077998	87	). UVM_INFO @ 43384568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	19465921353637620794390132222164635933694385042147995214164995125432690680190	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---