Simulation Results: rv_timer

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.18 %
  • code
  • 90.45 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 987.150us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 2.000s 124.321us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 22.489us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 1190.701us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 23.021us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 20.680us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 22.489us 1 1 100.00
rv_timer_csr_aliasing 1.000s 23.021us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 798.896us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 2314.518us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 101.000s 434607.406us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 101.000s 434607.406us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.000s 5200.056us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 2.000s 62.551us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 24.253us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 647.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 647.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 2.000s 124.321us 1 1 100.00
rv_timer_csr_rw 1.000s 22.489us 1 1 100.00
rv_timer_csr_aliasing 1.000s 23.021us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 22.979us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 2.000s 124.321us 1 1 100.00
rv_timer_csr_rw 1.000s 22.489us 1 1 100.00
rv_timer_csr_aliasing 1.000s 23.021us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 22.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 47.222us 1 1 100.00
rv_timer_tl_intg_err 1.000s 52.825us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 52.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 77.224us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 977.697us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 54.000s 43257.655us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 81008592090953752215235628039658119942176486914904706397394918093784814063017 85
UVM_INFO @ 77224405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 40231005059180792645704868610401593766884922877628862822326797980214381932918 84
UVM_INFO @ 977697369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---