Simulation Results: spi_device/1r1w

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.97 %
  • code
  • 89.53 %
  • assert
  • 95.52 %
  • func
  • 69.86 %
  • block
  • 98.37 %
  • line
  • 98.76 %
  • branch
  • 97.05 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 283.000s 30136.437us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 48.955us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 980.059us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 29.000s 2291.418us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 16.000s 861.230us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 189.687us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 980.059us 1 1 100.00
spi_device_csr_aliasing 16.000s 861.230us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 19.189us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 179.416us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 37.176us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 4.996us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.192us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 25.383us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 25.383us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 10.000s 16031.537us 1 1 100.00
spi_device_tpm_sts_read 2.000s 39.048us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 39.000s 17881.014us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.000s 99.770us 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.000s 3089.438us 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.000s 3089.438us 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 31.000s 2266.866us 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 31.000s 2266.866us 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 31.000s 2266.866us 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 31.000s 2266.866us 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 31.000s 2266.866us 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 7.000s 1560.677us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 8.000s 7468.824us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 8.000s 7468.824us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 8.000s 7468.824us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.000s 1034.322us 1 1 100.00
spi_device_read_buffer_direct 16.000s 3251.732us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 8.000s 7468.824us 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 175.000s 18178.568us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 10.000s 1026.597us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 10.000s 1026.597us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 67.000s 6044.630us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 283.000s 30136.437us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 0 1 0.00
spi_device_flash_and_tpm_min_idle 140.000s 9489.365us 0 1 0.00
stress_all 1 1 100.00
spi_device_stress_all 144.000s 43684.580us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 11.963us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 246.852us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.000s 255.870us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.000s 255.870us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 48.955us 1 1 100.00
spi_device_csr_rw 3.000s 980.059us 1 1 100.00
spi_device_csr_aliasing 16.000s 861.230us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 670.151us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 48.955us 1 1 100.00
spi_device_csr_rw 3.000s 980.059us 1 1 100.00
spi_device_csr_aliasing 16.000s 861.230us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 670.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 173.077us 1 1 100.00
spi_device_tl_intg_err 5.000s 110.707us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.000s 110.707us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 35778494729151889061246978054610608451069427863746553725907259823362311998690 87
UVM_ERROR @ 3595937 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[925] not found within the scope .
UVM_ERROR @ 3595937 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[925] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 29582482701646065398472135708570212251879638463091121675421468201152787222395 85
UVM_ERROR @ 931293 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x351 [1101010001] vs 0x0 [0])
UVM_ERROR @ 978293 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7e [1111110] vs 0x0 [0])
UVM_ERROR @ 1037293 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x37a [1101111010] vs 0x0 [0])
UVM_ERROR @ 1075293 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x27d [1001111101] vs 0x0 [0])
UVM_ERROR (spi_device_scoreboard.sv:2816) [scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == * (* [*] vs * [*]) 1 test run
spi_device_flash_and_tpm_min_idle 100570172408960705918537991320478131228852873023261001422596018576439032882931 131
UVM_INFO @ 9489365154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---