Simulation Results: sram_ctrl/ret

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.67 %
  • code
  • 82.40 %
  • assert
  • 97.81 %
  • func
  • 94.80 %
  • block
  • 93.89 %
  • line
  • 94.98 %
  • branch
  • 89.64 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 42.833us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 84.324us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.253us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 185.458us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 48.493us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 259.727us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.253us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 48.493us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 3045.016us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 342.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 16.000s 11477.290us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 92.000s 2009.380us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 149.095us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 1960.519us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 451.683us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 757.497us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 46.953us 1 1 100.00
sram_ctrl_partial_access_b2b 162.000s 47467.677us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 39.275us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 39.231us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 53.747us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 780.266us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 78.537us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 11.000s 1124.106us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 14.484us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 175.159us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 175.159us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 84.324us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.253us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 48.493us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 15.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 84.324us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.253us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 48.493us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 15.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 250.756us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 1198.843us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 538.341us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 1198.843us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 538.341us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 780.266us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 780.266us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.253us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 757.497us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 757.497us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 757.497us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 451.683us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 47.743us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 250.756us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 536.027us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 42.833us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 42.833us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 757.497us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 1198.843us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 451.683us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 1198.843us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1198.843us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 42.833us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1198.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 42.000s 4400.291us 1 1 100.00