Simulation Results: uart

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.43 %
  • code
  • 92.48 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 72.91 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 11.000s 5990.744us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 13.829us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 12.420us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 315.636us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 38.729us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 26.805us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 12.420us 1 1 100.00
uart_csr_aliasing 1.000s 38.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 13.000s 9125.138us 1 1 100.00
parity 2 2 100.00
uart_smoke 11.000s 5990.744us 1 1 100.00
uart_tx_rx 13.000s 9125.138us 1 1 100.00
parity_error 2 2 100.00
uart_intr 45.000s 31560.920us 1 1 100.00
uart_rx_parity_err 45.000s 76148.640us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 13.000s 9125.138us 1 1 100.00
uart_intr 45.000s 31560.920us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 90.000s 187591.691us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 10.000s 8406.178us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 127.000s 91129.946us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 45.000s 31560.920us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 45.000s 31560.920us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 45.000s 31560.920us 1 1 100.00
perf 1 1 100.00
uart_perf 97.000s 4694.456us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.000s 6926.743us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.000s 6926.743us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.000s 3342.616us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.000s 3259.916us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 26.000s 12550.685us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 6.000s 4038.883us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 677.000s 110795.425us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 90.000s 22616.907us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 18.610us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 12.590us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 3.000s 154.855us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 3.000s 154.855us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 13.829us 1 1 100.00
uart_csr_rw 1.000s 12.420us 1 1 100.00
uart_csr_aliasing 1.000s 38.729us 1 1 100.00
uart_same_csr_outstanding 2.000s 138.355us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 13.829us 1 1 100.00
uart_csr_rw 1.000s 12.420us 1 1 100.00
uart_csr_aliasing 1.000s 38.729us 1 1 100.00
uart_same_csr_outstanding 2.000s 138.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 1268.281us 1 1 100.00
uart_tl_intg_err 2.000s 528.613us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 528.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 14.000s 1802.047us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 32875539215815219673732956236718197576066977687896890609515569003076142801395 84
UVM_ERROR @ 3276615178 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3282258069 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3283258075 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3283972365 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0