Simulation Results: ac_range_check

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.89 %
  • code
  • 93.09 %
  • assert
  • 97.75 %
  • func
  • 57.84 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.09 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 28.000s 9218.556us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 44.000s 5162.619us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 1.000s 34.719us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 20.776us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 32.000s 12716.199us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 13.000s 1652.542us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 35.308us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 20.776us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 1652.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 1036.143us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 28.000s 6712.458us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 62.000s 2822.776us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 15.637us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 24.941us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 125.380us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 125.380us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 1.000s 34.719us 1 1 100.00
ac_range_check_csr_rw 2.000s 20.776us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 1652.542us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 627.589us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 1.000s 34.719us 1 1 100.00
ac_range_check_csr_rw 2.000s 20.776us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 1652.542us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 627.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 1693.553us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 1693.553us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 1693.553us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 1693.553us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 52.000s 1388.970us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 13.838us 1 1 100.00
ac_range_check_tl_intg_err 5.000s 235.331us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
ac_range_check_stress_all_with_rand_reset 93.000s 10626.545us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 24.000s 6299.367us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [ac_range_check_common_vseq] wait timeout occurred! 1 test run
ac_range_check_stress_all_with_rand_reset 5591950969851017278533214181149137684084236015753212029197074658407442639478 11224
UVM_INFO @ 10626545491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---