Simulation Results: alert_handler

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.49 %
  • code
  • 92.76 %
  • assert
  • 98.38 %
  • func
  • 80.32 %
  • line
  • 99.79 %
  • branch
  • 98.20 %
  • cond
  • 90.69 %
  • toggle
  • 91.24 %
  • FSM
  • 83.87 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 22.960s 1645.012us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.020s 78.055us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.890s 55.995us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 218.280s 12567.017us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 48.720s 4475.869us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.950s 587.150us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.890s 55.995us 1 1 100.00
alert_handler_csr_aliasing 48.720s 4475.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 31.760s 2298.566us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 48.680s 1253.504us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1784.600s 42578.401us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 49.090s 1322.463us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 22.960s 1645.012us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 19.040s 288.899us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 41.180s 1996.913us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 32.340s 4079.319us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1204.800s 19365.052us 1 1 100.00
alert_handler_lpg_stub_clk 1360.140s 61508.144us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2450.790s 219575.162us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 5.560s 107.592us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.130s 19.154us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.570s 12.768us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 9.030s 165.706us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 9.030s 165.706us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.020s 78.055us 1 1 100.00
alert_handler_csr_rw 2.890s 55.995us 1 1 100.00
alert_handler_csr_aliasing 48.720s 4475.869us 1 1 100.00
alert_handler_same_csr_outstanding 31.950s 2920.088us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.020s 78.055us 1 1 100.00
alert_handler_csr_rw 2.890s 55.995us 1 1 100.00
alert_handler_csr_aliasing 48.720s 4475.869us 1 1 100.00
alert_handler_same_csr_outstanding 31.950s 2920.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 143.470s 11586.926us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 143.470s 11586.926us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 143.470s 11586.926us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 143.470s 11586.926us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1088.780s 80671.300us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 34.630s 1096.932us 1 1 100.00
alert_handler_tl_intg_err 3.380s 74.662us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.380s 74.662us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 143.470s 11586.926us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 22.960s 1645.012us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 22.960s 1645.012us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 22.960s 1645.012us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 22.960s 1645.012us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 49.090s 1322.463us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1204.800s 19365.052us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 49.090s 1322.463us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1784.600s 42578.401us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1784.600s 42578.401us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 34.630s 1096.932us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 34.630s 1096.932us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 34.630s 1096.932us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 34.630s 1096.932us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 34.630s 1096.932us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 34.630s 1096.932us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 34.630s 1096.932us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 34.630s 1096.932us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 34.630s 1096.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 24.000s 1622.148us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 6379460208333596923193005296055373476421597637888192337657679631796836826149 90
UVM_INFO @ 4079319440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 40015028993953223785048095469706852722826902870292758550281784602013927567697 160
UVM_INFO @ 107592301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 105174100750604779419668610192385247618673528924594178887592810129501723848799 100
UVM_INFO @ 1622148093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---