| V1 |
|
27.27% |
| V2 |
|
32.16% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| unmapped |
|
40.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_uart_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 11.605s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rx_overflow | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 11.605s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rand_baudrate | 0 | 1 | 0.00 | |||
| chip_sw_uart_rand_baudrate | 35.411s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 28.576s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_out | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 355.730s | 293.220us | 1 | 1 | 100.00 | |
| chip_sw_gpio_in | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 355.730s | 293.220us | 1 | 1 | 100.00 | |
| chip_sw_gpio_irq | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 355.730s | 293.220us | 1 | 1 | 100.00 | |
| chip_sw_example_tests | 1 | 4 | 25.00 | |||
| chip_sw_example_rom | 37.890s | 10.200us | 0 | 1 | 0.00 | |
| chip_sw_example_manufacturer | 9.349s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_concurrency | 255.320s | 168.815us | 1 | 1 | 100.00 | |
| chip_sw_uart_smoketest_signed | 12.749s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| chip_csr_bit_bash | 8.840s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 9.390s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 9.390s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke | 1 | 1 | 100.00 | |||
| xbar_smoke | 33.570s | 71.222us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_spi_device_flash_mode | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 20.891s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_pass_through | 1 | 1 | 100.00 | |||
| chip_sw_spi_device_pass_through | 2811.170s | 4836.300us | 1 | 1 | 100.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 263.490s | 220.045us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_tpm | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_tpm | 13.596s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_spi_host_tx_rx | 10.600s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_host_tx_rx | 8.699s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_device_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_device_tx_rx | 10.032s | 0.000us | 0 | 1 | 0.00 | |
| chip_pin_mux | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 2.600s | 0.000us | 0 | 1 | 0.00 | |
| chip_padctrl_attributes | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 2.600s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_wake | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_wake | 10.436s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_retention | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_retention | 16.211s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 13.972s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_instruction_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 13.972s | 0.000us | 0 | 1 | 0.00 | |
| chip_jtag_csr_rw | 0 | 1 | 0.00 | |||
| chip_jtag_csr_rw | 103.730s | 131.355us | 0 | 1 | 0.00 | |
| chip_jtag_mem_access | 0 | 1 | 0.00 | |||
| chip_jtag_mem_access | 111.670s | 131.227us | 0 | 1 | 0.00 | |
| chip_rv_dm_ndm_reset_req | 1 | 1 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 327.080s | 309.867us | 1 | 1 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.243s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 9.914s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 0 | 1 | 0.00 | |||
| chip_rv_dm_lc_disabled | 93.920s | 124.507us | 0 | 1 | 0.00 | |
| chip_sw_timer | 1 | 1 | 100.00 | |||
| chip_sw_rv_timer_irq | 284.040s | 266.898us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_wakeup_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 481.290s | 504.273us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 481.290s | 504.273us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 1 | 1 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 429.960s | 386.530us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 206.480s | 182.467us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 206.480s | 182.467us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 1 | 1 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 396.860s | 2310.331us | 1 | 1 | 100.00 | |
| chip_sw_plic_sw_irq | 1 | 1 | 100.00 | |||
| chip_sw_plic_sw_irq | 179.910s | 164.421us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 4 | 4 | 100.00 | |||
| chip_sw_otbn_randomness | 285.190s | 245.006us | 1 | 1 | 100.00 | |
| chip_sw_aes_idle | 197.380s | 165.832us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc_idle | 200.780s | 178.088us | 1 | 1 | 100.00 | |
| chip_sw_kmac_idle | 197.680s | 164.113us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_off_trans | 0 | 4 | 0.00 | |||
| chip_sw_clkmgr_off_aes_trans | 199.220s | 185.360us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_hmac_trans | 207.090s | 185.296us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_kmac_trans | 212.410s | 185.440us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_otbn_trans | 210.410s | 185.232us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 1 | 7 | 14.29 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 40.740s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 40.610s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 40.230s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 38.530s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 45.660s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.479s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 191.190s | 161.301us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_extended_range | 1 | 8 | 12.50 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 426.400s | 1962.968us | 1 | 1 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 40.620s | 10.240us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 40.490s | 10.100us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 39.580s | 10.340us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 40.510s | 10.140us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 41.190s | 10.400us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 40.130s | 10.160us | 0 | 1 | 0.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 40.540s | 10.320us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 12.527s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_sleep_frequency | 10.080s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_reset_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_reset_frequency | 9.512s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1027.330s | 943.638us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 133.850s | 118.473us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_all_reset_reqs | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 206.480s | 182.467us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_wdog_reset | 13.818s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 133.850s | 118.473us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 12.658s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 24.471s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 11.420s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 9.639s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_disabled | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 9.490s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1027.330s | 943.638us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sys_reset_info | 1 | 1 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 327.080s | 309.867us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 391.310s | 412.064us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_req_reset | 1 | 1 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 337.370s | 305.280us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_alert_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 381.910s | 331.143us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_rst | 1 | 1 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 182.070s | 163.743us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1027.330s | 943.638us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_test | 10.133s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_escalations | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 38.642s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_all_escalation_resets | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1027.330s | 943.638us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_entropy | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_entropy | 41.681s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_crashdump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 381.910s | 331.143us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_ping_timeout | 1 | 1 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 306.310s | 302.587us | 1 | 1 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 74.960s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 80.411s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 83.563s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 77.157s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 87.119s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 38.642s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_jtag_access | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 14.259s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 8.889s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 14.259s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transitions | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 14.259s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_kmac_req | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 14.259s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_key_div | 1 | 1 | 100.00 | |||
| chip_sw_keymgr_dpe_key_derivation_prod | 386.460s | 351.325us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_broadcast | 1 | 10 | 10.00 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.552s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 10.989s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 10.111s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 9.356s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 14.259s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation | 364.220s | 351.124us | 1 | 1 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 178.930s | 157.224us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_execution_main | 10.145s | 0.000us | 0 | 1 | 0.00 | |
| chip_prim_tl_access | 89.450s | 117.432us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 93.920s | 124.507us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc | 1 | 2 | 50.00 | |||
| chip_sw_aes_enc | 189.780s | 173.008us | 1 | 1 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 40.610s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_aes_gcm | 1 | 2 | 50.00 | |||
| chip_sw_aes_enc | 189.780s | 173.008us | 1 | 1 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 40.610s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_aes_entropy | 1 | 1 | 100.00 | |||
| chip_sw_aes_entropy | 176.370s | 164.538us | 1 | 1 | 100.00 | |
| chip_sw_aes_idle | 1 | 1 | 100.00 | |||
| chip_sw_aes_idle | 197.380s | 165.832us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc | 1 | 2 | 50.00 | |||
| chip_sw_hmac_enc | 199.140s | 173.762us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 40.230s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_hmac_idle | 1 | 1 | 100.00 | |||
| chip_sw_hmac_enc_idle | 200.780s | 178.088us | 1 | 1 | 100.00 | |
| chip_sw_kmac_enc | 2 | 3 | 66.67 | |||
| chip_sw_kmac_mode_cshake | 210.980s | 167.380us | 1 | 1 | 100.00 | |
| chip_sw_kmac_mode_kmac | 220.400s | 188.898us | 1 | 1 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 45.660s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_keymgr | 1 | 1 | 100.00 | |||
| chip_sw_keymgr_dpe_key_derivation | 364.220s | 351.124us | 1 | 1 | 100.00 | |
| chip_sw_kmac_app_lc | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 14.259s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_rom | 0 | 1 | 0.00 | |||
| chip_sw_kmac_app_rom | 15.676s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_entropy | 1 | 1 | 100.00 | |||
| chip_sw_kmac_entropy | 300.220s | 238.034us | 1 | 1 | 100.00 | |
| chip_sw_kmac_idle | 1 | 1 | 100.00 | |||
| chip_sw_kmac_idle | 197.680s | 164.113us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_csrng | 1 | 1 | 100.00 | |||
| chip_sw_entropy_src_csrng | 1645.300s | 2224.252us | 1 | 1 | 100.00 | |
| chip_sw_csrng_edn_cmd | 1 | 1 | 100.00 | |||
| chip_sw_entropy_src_csrng | 1645.300s | 2224.252us | 1 | 1 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 0 | 1 | 0.00 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 10.128s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_known_answer_tests | 1 | 1 | 100.00 | |||
| chip_sw_csrng_kat_test | 212.530s | 175.980us | 1 | 1 | 100.00 | |
| chip_sw_edn_entropy_reqs | 1 | 1 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 2764.340s | 1790.179us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 1 | 2 | 50.00 | |||
| chip_sw_keymgr_dpe_key_derivation | 364.220s | 351.124us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 38.530s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_otbn_op | 1 | 2 | 50.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 3241.310s | 1493.381us | 1 | 1 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 40.740s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_otbn_rnd_entropy | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 285.190s | 245.006us | 1 | 1 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 285.190s | 245.006us | 1 | 1 | 100.00 | |
| chip_sw_otbn_idle | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 285.190s | 245.006us | 1 | 1 | 100.00 | |
| chip_sw_otbn_mem_scramble | 1 | 1 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 406.100s | 280.599us | 1 | 1 | 100.00 | |
| chip_sw_rom_access | 0 | 1 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 178.930s | 157.224us | 0 | 1 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 0 | 1 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 178.930s | 157.224us | 0 | 1 | 0.00 | |
| chip_sw_sram_scrambled_access | 1 | 2 | 50.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 411.880s | 350.189us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.479s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_execution | 0 | 1 | 0.00 | |||
| chip_sw_sram_ctrl_execution_main | 10.145s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_lc_escalation | 0 | 2 | 0.00 | |||
| chip_sw_all_escalation_resets | 1027.330s | 943.638us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity_escalation | 13.972s | 0.000us | 0 | 1 | 0.00 | |
| chip_otp_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 14.259s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_keys | 4 | 4 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 406.100s | 280.599us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 364.220s | 351.124us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 411.880s | 350.189us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 205.490s | 175.973us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 4 | 4 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 406.100s | 280.599us | 1 | 1 | 100.00 | |
| chip_sw_keymgr_dpe_key_derivation | 364.220s | 351.124us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 411.880s | 350.189us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 205.490s | 175.973us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_program | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 14.259s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_program_error | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_program_error | 13.183s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 8.889s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals | 0 | 6 | 0.00 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.552s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 10.989s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 10.111s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 9.356s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 14.259s | 0.000us | 0 | 1 | 0.00 | |
| chip_prim_tl_access | 89.450s | 117.432us | 0 | 1 | 0.00 | |
| chip_sw_otp_prim_tl_access | 0 | 1 | 0.00 | |||
| chip_prim_tl_access | 89.450s | 117.432us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_nvm_cnt | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_nvm_cnt | 9.820s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_sw_parts | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_sw_parts | 15.111s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_clk_outputs | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 12.527s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 1 | 7 | 14.29 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 40.740s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 40.610s | 10.380us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 40.230s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 38.530s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 45.660s | 10.180us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.479s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 191.190s | 161.301us | 1 | 1 | 100.00 | |
| chip_sw_soc_proxy_external_reset_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 176.660s | 156.160us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_irqs | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 176.660s | 156.160us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_wakeup_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_external_wakeup | 205.470s | 157.861us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_gpios | 1 | 1 | 100.00 | |||
| chip_sw_soc_proxy_gpios | 199.730s | 172.109us | 1 | 1 | 100.00 | |
| chip_sw_nmi_irq | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 413.570s | 269.232us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_rnd | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_rnd | 220.850s | 178.638us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_address_translation | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 219.260s | 179.950us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 205.490s | 175.973us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 391.310s | 412.064us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_double_fault | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 391.310s | 412.064us | 0 | 1 | 0.00 | |
| chip_sw_smoketest | 14 | 14 | 100.00 | |||
| chip_sw_aes_smoketest | 193.230s | 173.108us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_smoketest | 192.570s | 182.383us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_smoketest | 213.380s | 162.118us | 1 | 1 | 100.00 | |
| chip_sw_csrng_smoketest | 204.510s | 164.217us | 1 | 1 | 100.00 | |
| chip_sw_gpio_smoketest | 215.740s | 192.920us | 1 | 1 | 100.00 | |
| chip_sw_hmac_smoketest | 247.790s | 194.812us | 1 | 1 | 100.00 | |
| chip_sw_kmac_smoketest | 242.070s | 185.504us | 1 | 1 | 100.00 | |
| chip_sw_otbn_smoketest | 263.960s | 213.241us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_smoketest | 177.000s | 165.804us | 1 | 1 | 100.00 | |
| chip_sw_rv_plic_smoketest | 193.660s | 163.980us | 1 | 1 | 100.00 | |
| chip_sw_rv_timer_smoketest | 285.760s | 266.890us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_smoketest | 197.510s | 160.936us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 192.680s | 164.433us | 1 | 1 | 100.00 | |
| chip_sw_uart_smoketest | 211.270s | 175.208us | 1 | 1 | 100.00 | |
| chip_sw_rom_functests | 0 | 1 | 0.00 | |||
| rom_keymgr_functest | 9.146s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_signed | 0 | 1 | 0.00 | |||
| chip_sw_uart_smoketest_signed | 12.749s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_boot | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 20.891s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_secure_boot | 0 | 1 | 0.00 | |||
| base_rom_e2e_smoke | 8.316s | 0.000us | 0 | 1 | 0.00 | |
| chip_lc_scrap | 0 | 4 | 0.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 204.620s | 172.888us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 158.460s | 171.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 146.200s | 172.024us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 179.370s | 171.512us | 0 | 1 | 0.00 | |
| chip_lc_test_locked | 0 | 2 | 0.00 | |||
| chip_sw_lc_walkthrough_testunlocks | 15.794s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 93.920s | 124.507us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough | 0 | 5 | 0.00 | |||
| chip_sw_lc_walkthrough_dev | 66.089s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 46.320s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 11.779s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_rma | 18.291s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 15.794s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 0 | 3 | 0.00 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 263.880s | 348.520us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 476.110s | 546.952us | 0 | 1 | 0.00 | |
| rom_volatile_raw_unlock | 8.367s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_raw_unlock | 0 | 1 | 0.00 | |||
| rom_raw_unlock | 8.862s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 0 | 1 | 0.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 19.619s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_inject_scramble_seed | 0 | 1 | 0.00 | |||
| chip_sw_inject_scramble_seed | 74.543s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 106.760s | 117.777us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 106.760s | 117.777us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 9.390s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 8.820s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 9.390s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 8.820s | 0.000us | 0 | 1 | 0.00 | |
| xbar_base_random_sequence | 1 | 1 | 100.00 | |||
| xbar_random | 49.050s | 43.531us | 1 | 1 | 100.00 | |
| xbar_random_delay | 6 | 6 | 100.00 | |||
| xbar_smoke_zero_delays | 10.120s | 13.616us | 1 | 1 | 100.00 | |
| xbar_smoke_large_delays | 202.390s | 1989.003us | 1 | 1 | 100.00 | |
| xbar_smoke_slow_rsp | 289.180s | 1830.439us | 1 | 1 | 100.00 | |
| xbar_random_zero_delays | 97.080s | 74.617us | 1 | 1 | 100.00 | |
| xbar_random_large_delays | 1236.110s | 12183.707us | 1 | 1 | 100.00 | |
| xbar_random_slow_rsp | 219.670s | 1368.634us | 1 | 1 | 100.00 | |
| xbar_unmapped_address | 2 | 2 | 100.00 | |||
| xbar_unmapped_addr | 49.440s | 31.256us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 39.960s | 67.404us | 1 | 1 | 100.00 | |
| xbar_error_cases | 2 | 2 | 100.00 | |||
| xbar_error_random | 213.750s | 511.687us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 39.960s | 67.404us | 1 | 1 | 100.00 | |
| xbar_all_access_same_device | 2 | 2 | 100.00 | |||
| xbar_access_same_device | 54.250s | 135.759us | 1 | 1 | 100.00 | |
| xbar_access_same_device_slow_rsp | 3195.470s | 20938.393us | 1 | 1 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 1 | 1 | 100.00 | |||
| xbar_same_source | 32.760s | 27.890us | 1 | 1 | 100.00 | |
| xbar_stress_all | 2 | 2 | 100.00 | |||
| xbar_stress_all | 56.840s | 43.260us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_error | 597.830s | 559.923us | 1 | 1 | 100.00 | |
| xbar_stress_with_reset | 2 | 2 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 2107.130s | 3510.570us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_reset_error | 750.430s | 702.399us | 1 | 1 | 100.00 | |
| rom_e2e_smoke | 0 | 1 | 0.00 | |||
| rom_e2e_smoke | 9.328s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_output | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_output | 26.815s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_exception_c | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_exception_c | 21.238s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 40.624s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 9.622s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 8.729s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 8.739s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 8.602s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 44.926s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 9.793s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 8.954s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 10.112s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 8.922s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 118.889s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 13.368s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 10.396s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 11.044s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 11.711s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 135.903s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 25.279s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 11.939s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 13.400s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 9.878s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 90.161s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 19.154s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 17.082s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 13.673s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 18.976s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 17.642s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 15.921s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 17.280s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 16.210s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 11.986s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 5 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 52.553s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_dev | 15.537s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod | 11.185s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod_end | 10.728s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_rma | 12.224s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init | 0 | 3 | 0.00 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 12.816s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 20.231s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 22.293s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_static_critical | 0 | 1 | 0.00 | |||
| rom_e2e_static_critical | 8.340s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 1 | 1 | 100.00 | |||
| chip_sw_aes_masking_off | 251.230s | 196.125us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 168.740s | 136.876us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 10.321s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 14.403s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 19.131s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 12.146s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_plic_alerts | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1027.330s | 943.638us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 12.779s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 211.700s | 176.936us | 0 | 1 | 0.00 | |
| chip_sw_coremark | 0 | 1 | 0.00 | |||
| chip_sw_coremark | 12.321s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_power_max_load | 0 | 1 | 0.00 | |||
| chip_sw_power_virus | 92.889s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 10.321s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 14.403s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 19.131s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 15.678s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 9.389s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 17.059s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 1 | 0.00 | |||
| rom_e2e_self_hash | 113.265s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 8 | 20 | 40.00 | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 40.000s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_aes_gcm | 257.050s | 203.463us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_kat_test | 176.680s | 163.574us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 180.170s | 161.126us | 1 | 1 | 100.00 | |
| chip_plic_all_irqs_0 | 435.500s | 327.587us | 1 | 1 | 100.00 | |
| chip_plic_all_irqs_10 | 437.740s | 300.631us | 1 | 1 | 100.00 | |
| chip_sw_dma_inline_hashing | 247.770s | 208.622us | 1 | 1 | 100.00 | |
| chip_sw_dma_abort | 290.840s | 211.731us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 15.135s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 12.256s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_otbn | 12.079s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_sw | 10.555s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_otbn | 9.602s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_sw | 8.498s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 9.625s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_sw | 9.372s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_otbn | 8.157s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_sw | 8.255s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_smoketest | 261.490s | 190.652us | 1 | 1 | 100.00 | |
| chip_sw_mbx_smoketest | 489.580s | 421.682us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 119 test runs | |||
| chip_sw_example_manufacturer | 12526569444532542895726181028649848075797321156954368043290749883166945309835 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.234s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_data_integrity_escalation | 55426350316390106785551934874051328139325764407110665324728296940636380126630 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.731s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sleep_pin_wake | 49346768055151836780032855259113634983205971686735644212246937250808397387135 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.283s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sleep_pin_retention | 69200222426666339562513385206534150121618386271839613988640580452143349128301 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.150s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx | 48570941927853773849261312646341087842221794156352954862949510863386274114068 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.585s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx_bootstrap | 65921279114729526780728512386637920184731908845108136190473914675870769708546 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.702s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_inject_scramble_seed | 13718062832135073533492890911296167964948267357704425568593998786270351860505 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.867s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_exit_test_unlocked_bootstrap | 61000084736275933356514623118765208128008135035518015505754628430582386885493 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.788s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_rand_baudrate | 23139589502424992320994006149713829582553699683046735823097881994960611291524 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 12.930s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx_alt_clk_freq | 1055908766332657234581070816882024639114210029839881883380442082388343297042 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.727s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_i2c_host_tx_rx | 41161051208309648270795280047840716237616506496227692960971625294982640990394 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.288s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_i2c_device_tx_rx | 47246416238549667877523772333486059049935975061258706583902536672948099280382 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.261s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_spi_device_tpm | 108321917298174159921598007409488888219801983278105161127499905371866133274677 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.133s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_spi_host_tx_rx | 114333737309488037400430689946946064166309005930763323931028865849791094063608 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.332s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_otp_hw_cfg | 47062560421720804420740636165445667402143784076395875591133443357780159045730 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 49196462338702524580896856450323279642368350689254272562605856053395729286441 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.256s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_dev | 70141137439493719580232135187728414145219433895914254988461149060066150949573 | None |
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.856s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_prod | 21894093652582354129142609732453159933863593999486028456487547086973502478973 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.284s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 5254144299833732096556390329321419169422266596530724710055007632019250011696 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.278s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_vendor_test_csr_access | 17494611097931750076123255197826633237279653472596411560417520767065707578394 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.814s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_nvm_cnt | 105111108736978006562368353163094129311543124442932254107351967216532105970003 | None |
---- STDERR ----
Another command (pid=491203) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_sw_parts | 32903021394664800544166501519881163930331406283221917828396744049222416840890 | None |
Another command (pid=478478) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=503560) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=485401) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_transition | 104474248266198456505731858741799306405649566029791312464484611449974806312430 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.686s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_dev | 29933998599214981946651415473873386026444357484122636226997588338253567474132 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.146s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_prod | 40336137539759916655070551039678578764549975878584302525088369998126577694097 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 9.308s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_prodend | 18914259344823873531295005203207076278304209527365294862403378471696194354597 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.621s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_rma | 97752991138874454287343683695504439152292517129520163046093023497263634392017 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.166s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_testunlocks | 60358099882998097064874791203225491176368968411035723873527590335552742029338 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.967s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_main_power_glitch_reset | 68446849150290564238906065777404056595121470908472190885829424445753891261285 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.652s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 95459340298170773440808705672664424308157571460272140849710116325198762254604 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.257s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 90020360756095565665409881976019924025500679697026443861102185029827939797620 | None |
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.065s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 7429773901828278141528639688128807570839001321341273907784453090609844966525 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.659s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_disabled | 15775101593558523961548346416681597103921529650777581396141843528655084670879 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.261s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_wdog_reset | 60191436183928670493196332189731886287681490220682442040402063539458749206975 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.196s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_test | 98178579528620235512626015764516159767917564489250612596705895982846557281350 | None |
Another command (pid=736681) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_escalation | 76530259254354745716889841296415627912676818527745217129218204050593645925815 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.143s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 75680582948400952850620273269499048935662634223662555697979911267613388798038 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 12.261s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 99219756276047003438314307687530993224815941648298446436959565620679458336863 | None |
Another command (pid=462994) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=469371) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=468424) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_sleep_mode_pings | 103028580654383373446380417586891973739441490303670005624607011451120896053391 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.773s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_clkoff | 92839625836021206897817752855784608862048263257022463543057820408199810032829 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 9.449s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_reset_toggle | 10949924713250985536511353486813490459967884533810851190213029966168611443059 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.207s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_entropy | 46861240263463954736683248664435527763388116209031807739305287658061559428062 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 25.775s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 105554353759085261268873698512085349983175147826952010762347358451054933822847 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.287s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_kmac_app_rom | 104455327651316871672531341323072105994681393180839093072547742597435846048825 | None |
---- STDERR ----
Another command (pid=1145361) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).
DEBUG: /nightly/current_run/opentitan/rules/autogen.bzl:536:14: NOTE: stamping is disabled, the build_info section will use a fixed version string
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 91448684610969110638092856936821766381233641096007141103703438261197823060323 | None |
---- STDERR ----
Another command (pid=1373522) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sram_ctrl_execution_main | 101649514357550273773601970178293280426545935895007397269400519097622093778201 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.294s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_coremark | 70808075596467813512615560340360716413566712837914045980509964946996144663507 | None |
Another command (pid=493263) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_clkmgr_reset_frequency | 95838316465613854582712861855407681733981476377415844657687894349722466220753 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_reset_frequency_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.320s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_clkmgr_sleep_frequency | 10315825354078278185229776997430092920865063643965730553400142447185081163913 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.249s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_ast_clk_outputs | 9287478300583241175082767102084229863865361256584892971401490929169852774973 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:ast_clk_outs_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.420s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_program_error | 44854355521593184163219408955179227318024435232722637874943467440442962248752 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.643s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 44936325793339738263208349878133946812556750377389706493662066974229272977488 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_access_after_wakeup | 35531229413319295376127947812202409157587781943590107560152888538576258630504 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_access_after_escalation_reset | 49038547824379593092745344190445735610263880213106165442608665616608113336375 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.642s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_power_virus | 58621611632598116914370960834417301388306215378610839377765454890108504656681 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:power_virus_systemtest_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.631s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| base_rom_e2e_smoke | 106974456822122705966321675587294028068714281461129959447495929154272143174305 | None |
_deploy_software_collateral(args)
~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 329, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 261, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
^^^^^^^^^^^^^^^^^^^
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_smoke | 67028258276941914821732262210496314171295513681262266444886200891916351222132 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_shutdown_exception_c | 52418169961115525230341002427624434493125283372704809072233414843439260391735 | None |
Another command (pid=563534) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=563100) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=564491) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_shutdown_output | 110490183082766575635512313303352463631197840782492848729791007160736572859932 | None |
Another command (pid=584671) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=579913) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=583003) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 35681294610843026471162478443413407236052504671093710305069108249961981790716 | None |
---- STDERR ----
Another command (pid=279368) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 20715912247208389065208396142503558824785002388596810238218063057136672255581 | None |
---- STDERR ----
Another command (pid=511245) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=516522) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 79476588971020742532114557704609851695516271110965556942770722526206703155549 | None |
---- STDERR ----
Another command (pid=516522) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 26880711936043352776855867445076499364746089025210497124342260647644237227224 | None |
---- STDERR ----
Another command (pid=519792) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 17525982239901970852572412973184682620449565239619284528982179970921803456212 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 114834470815974261957941918487320232771177091768185662901895289758146363346073 | None |
Another command (pid=350892) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=342046) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=302495) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 28945785812752288399024246142232719513095558396155752225533145967920708668257 | None |
---- STDERR ----
Another command (pid=516936) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 71976421687718158186466518057228328973432624121744655650684132338214555228124 | None |
---- STDERR ----
Another command (pid=518373) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 55163445595603579649376152762224004588595277426020242414404331602142552395186 | None |
Another command (pid=518373) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=516522) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=519538) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 30826845034310764557718531205759948797120122253308144132308489599994051135661 | None |
---- STDERR ----
Another command (pid=518373) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 80323532389979135065686370440085791265752769254429166326302850378282839528499 | None |
Another command (pid=375571) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=359742) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=369378) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 94482411412910552328127553154229709553421078878902290622252836324437369342915 | None |
Another command (pid=518373) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=516522) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=519538) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 60019038578691625625601395607289842519861656553006557639391442443520253288613 | None |
---- STDERR ----
Another command (pid=496348) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 18158667753226396631703577962683680510938924859450446289847837122702648063367 | None |
Another command (pid=511634) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=516936) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=518373) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 74687525040651930309294354875540694950551403203379559145527039490107694751819 | None |
---- STDERR ----
Another command (pid=519538) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 40436284570577305987499820823074193209793286558869337889805336947755602929049 | None |
---- STDERR ----
Another command (pid=353425) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 105195837478586349433791213171689183385888923597690787437967929606674635750375 | None |
Another command (pid=577495) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=545299) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=592185) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 49388594517971357175594265937744717508392914606771886861230480359504830619411 | None |
---- STDERR ----
Another command (pid=568370) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 75869595380517293901427121525601391045046788232420647536989647051314977989800 | None |
---- STDERR ----
Another command (pid=549010) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=581909) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 106397196712362792046062156906701246514968373775539368286473172576313837921798 | None |
---- STDERR ----
Another command (pid=558345) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 107295279081885256033369042400718493218892422775392868303656853260474931070731 | None |
Another command (pid=375571) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=370670) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=452068) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 31656144461984761156696450289841069105796603027668824731889936888572494981122 | None |
Another command (pid=602174) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=594841) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=600988) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 16648915949460332437664761227539220599565310328775486823842793110646192845761 | None |
Another command (pid=603432) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=600136) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=602174) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 36806910946697785335610586012429778073705826540436976139877832359664293975625 | None |
---- STDERR ----
Another command (pid=596177) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=573117) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 55959710735541732113863140220445179101703665195620140902253987554014062939354 | None |
Another command (pid=618457) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=616619) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=622960) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 105223414737233560170177967687751471610798662987787140958994314626431988604519 | None |
---- STDERR ----
Another command (pid=301141) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 12138074737589581878946611336855826079660653191395071059327902968566712652415 | None |
Another command (pid=602174) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=594841) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=600988) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 18793336412913045500284653302231433773180454255104483162919028024627094711928 | None |
Another command (pid=613250) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=613585) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=610013) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 94280563577195239973313510201000377254338418660619728997379380613331257021494 | None |
Another command (pid=600988) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=613250) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=613585) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 111719658722020622779715273860988758589186397395586984986152981378808761378124 | None |
Another command (pid=602174) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=594841) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=600988) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 93591138937854534983052199587430715482381009724276422485036960166004669892119 | None |
Another command (pid=310160) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=350892) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=342046) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 9002216896724389399283342793964306933642112202831053982957901459026381957353 | None |
Another command (pid=494438) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=504996) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=510832) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 62237731067312442637987634271934734372959713410214593439993138787905346898134 | None |
Another command (pid=502530) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=485401) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=494438) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 44395928668605303965223492229475128842931008114751551141519766734273059687020 | None |
Another command (pid=494438) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=508774) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=510832) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 72434176117812196698533667967041749634404277767576359300310709548576411247907 | None |
Another command (pid=511134) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=516936) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=518373) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_test_unlocked0 | 62343693398195938407947422325951357373590114071094110843148659556577594200590 | None |
Another command (pid=535142) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=538491) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=534001) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_dev | 65614760960147304476690605348132807217556483126878273027254197715342960362330 | None |
Another command (pid=539058) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=533224) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=537663) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_rma | 58701123931937353708537390126718830768483232434101129927748616814446674077701 | None |
Another command (pid=551653) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=557341) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=533603) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 36141154678084893599524110059581068952962854065058109275383810587814919316917 | None |
Another command (pid=477978) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=468883) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=490654) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_dev | 77427951206943103919462338991446425198085369927956452193778400123795534717771 | None |
Another command (pid=462994) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=469371) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=468424) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_rma | 104174615748089672936025845281794578049241601831883746468937782033523137391899 | None |
Another command (pid=489978) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=490654) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=491203) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_static_critical | 12719871414056131160503939079119575327086958471517650037691499420427551535558 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_meas | 62539230040318906318146217843951384117302151209096726947914280968928278901236 | None |
Another command (pid=534001) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=541877) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=533224) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_no_meas | 64056660079570437398474563814014212894279799587102391678759987047264672665531 | None |
Another command (pid=538670) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=540623) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=563534) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 75002496027258579543173395694357564004638314937210283372322328138545409222112 | None |
Another command (pid=563100) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=544661) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=540325) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 104768568274171647159915214095941098363410515593394318954315936414736232092339 | None |
Another command (pid=279368) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=349401) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=350892) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 93632751925543468964243944229566720733362202873502045570415964392259179512490 | None |
Another command (pid=349401) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=350892) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=342046) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_dev_otbn | 5867270198916909853676926366548924545085197041976050179129456718979986532963 | None |
Another command (pid=600988) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=613250) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=613585) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_dev_sw | 82440957605191137176047865117726849793227704335077339197090393567163739515418 | None |
Another command (pid=600988) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=613250) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=613585) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_otbn | 8494932417013264410368024728299516216544258485533428749449379789886126532854 | None |
Another command (pid=600988) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=596966) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=613250) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_sw | 69211116405917178226591599187388512319806290083112613111064683928759743392258 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 11573657233112450757179180491849138258204467227863864176128310612920259264556 | None |
Another command (pid=594841) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=600988) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=611867) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_end_sw | 87738956158697406386251296104077860172043914030909791971139665267021729788751 | None |
Another command (pid=594841) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=600988) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=613250) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_rma_otbn | 61263430402353121014388226793810005720469240397474752918152609554773698709571 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_rma_sw | 22289863834035395199137536449080290365009168173248737906339128066024722963491 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 104549041599522854665434966890344140657051256373962187122302236242500295463859 | None |
---- STDERR ----
Another command (pid=356151) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 492632842303411220192172833569051152946567922969159350976970249155746491165 | None |
---- STDERR ----
Another command (pid=279368) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 112811241976165906857716080751584292346759746664577757688522780386786280208130 | None |
Another command (pid=463992) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=375383) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=462994) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_smoketest_signed | 27052563722467164111544439727489716558002159792073196112564630119941429793426 | None |
Another command (pid=449506) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=499112) is running. Waiting for it to complete on the server (server_pid=203115)...
Another command (pid=478478) is running. Waiting for it to complete on the server (server_pid=203115)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_keymgr_functest | 8757241875439606761574392247217249405086298174267264692600012401051337345712 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (f2055d) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.318s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| UVM_FATAL @ * us: (dv_utils_pkg.sv:253) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" | 12 test runs | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 42675938325929288553646998737704396557178319981752638124382872387641883312198 | 318 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aes_enc_jitter_en | 34881567095287247025622673131791539591797038243695144322411484200812399584891 | 318 |
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_enc_jitter_en | 71527493014884950489146815850922463968620396867404377363439790293481291583441 | 318 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 20370501344065223033126789321433544555303068391485645070962867059589377479886 | 318 |
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_kmac_mode_kmac_jitter_en | 91017592196670940814158076997061280086131686911035078498104499130436865400271 | 318 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 97362626659467120290865321663880520344251577627994600959879471219290968188051 | 318 |
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aes_enc_jitter_en_reduced_freq | 55127021248992201612518230807013197452486615405072158296057537115002639942172 | 318 |
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_enc_jitter_en_reduced_freq | 67039020338461073268844833497923077638133471058193157380376702791100369181976 | 318 |
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 6313829846729342689184450185036035643337253609856772298378886774797647943341 | 318 |
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 70066589003081927075026807980668754153448827604710917415896694671675744662524 | 318 |
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 41465705894573062526938361345343633050124973615627989192707921425647156501300 | 318 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_edn_concurrency_reduced_freq | 70434320644231821041922274388071254442115750222090024203085915693791281099623 | 318 |
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((~rst_ni) === (~seed_en_q))' | 9 test runs | |||
| chip_sw_lc_ctrl_rma_to_scrap | 41294143775998026668155166689466408068845602659440697784622158588897065515749 | 339 |
UVM_ERROR @ 172.888000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 172.888000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_ctrl_raw_to_scrap | 46390603999405054129058999875795801535497179429671566736132098684685144152016 | 328 |
UVM_ERROR @ 171.000000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 171.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_ctrl_test_locked0_to_scrap | 95872101363975208960791326887495873881329071292964048412582969601944435602323 | 328 |
UVM_ERROR @ 172.024000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 172.024000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_ctrl_rand_to_scrap | 60190271661543868039648082623928724980822527663795767662194562355065145167523 | 328 |
UVM_ERROR @ 171.512000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 171.512000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_ctrl_volatile_raw_unlock | 8698594032794978477588663142420865711663522805645360195481496624366491486849 | 331 |
UVM_ERROR @ 348.520000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 348.520000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 92684070197018118831505319618919661850921427931349604353109650624060479906807 | 334 |
UVM_ERROR @ 546.952000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 546.952000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_sw_pwrmgr_full_aon_reset | 77242992121284989752227679158376101622432162046874170662338250554968626599228 | 321 |
UVM_ERROR @ 118.473000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 118.473000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_sw_rom_ctrl_integrity_check | 30789525636209209900845567800207442971163841754645339069489079125173430508646 | 330 |
UVM_ERROR @ 157.224000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 157.224000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_prim_tl_access | 57463146291311095273701273313986094311768146999569937526127459700473544599672 | 240 |
UVM_ERROR @ 117.432000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 117.432000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((!rstreqs[*]) && (reset_cause != HwReq))' | 5 test runs | |||
| chip_sw_rstmgr_cpu_info | 100439221052085363994900192133701491086429478213570500927517191200836922363648 | 352 |
UVM_ERROR @ 412.064000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 412.064000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_sw_clkmgr_off_aes_trans | 52466349268221808873490608984740419267040208001514508340694076346959079542261 | 329 |
UVM_ERROR @ 185.360000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.360000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_sw_clkmgr_off_hmac_trans | 84595868326546705666706989912534820712366744204552494921756114586548104146318 | 329 |
UVM_ERROR @ 185.296000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.296000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_sw_clkmgr_off_kmac_trans | 77652924354153508731315102828653489136620091429926264608645492046091431730587 | 329 |
UVM_ERROR @ 185.440000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_sw_clkmgr_off_otbn_trans | 85017025328908268254288057862553574963024156112927197752114456788058729673703 | 329 |
UVM_ERROR @ 185.232000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.232000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode | 3 test runs | |||
| chip_csr_bit_bash | 5258498656131383017534857375415256320296521541037738712968832088527832191072 | 142 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_aliasing | 112200504218902195651238223185382870256505616321311136307392319479145246822884 | 142 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_same_csr_outstanding | 106499231306784071042397024587893275959198341135451698858800702707364794090181 | 142 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR @ * us: (jtag_riscv_driver.sv:221) [jtag_riscv_agent_pkg] Check failed sbcs_val[SbAccess32] == * (* [*] vs * [*]) expect SBA width to be * bits! | 2 test runs | |||
| chip_jtag_csr_rw | 76582131859687979862786364083241164202417514392581609543776192416357358514632 | 5962 |
UVM_INFO @ 131.355000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_jtag_mem_access | 19934968331008730911260766733635275527309172889259447891974200105769773546320 | 5962 |
UVM_INFO @ 131.227000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode | 1 test run | |||
| chip_sw_example_rom | 56347975797795766793198341676427364861646678328417758440067703299127632530343 | 290 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size | 1 test run | |||
| chip_sw_all_escalation_resets | 64413527931624418436158299586570627656680946402622147022843624051256233214968 | 358 |
UVM_INFO @ 943.638000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path | 1 test run | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 75620973076784088368640850303862994336620425070649122607634367434763571917920 | 319 |
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | 1 test run | |||
| chip_sw_spi_device_pass_through_collision | 105287132953244397062290777511166066627271327805103063222887742720012572330425 | 340 |
UVM_INFO @ 220.045000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | 1 test run | |||
| chip_sw_otp_ctrl_escalation | 23366553161630205329597851255579837284050209616173313848696602682321645045824 | 334 |
UVM_ERROR @ 176.936000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 176.936000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size | 1 test run | |||
| chip_sw_rstmgr_alert_info | 105103675594468502445935856836606335816707136698716874977421362776842998139526 | 348 |
UVM_INFO @ 331.143000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! | 1 test run | |||
| chip_sw_soc_proxy_smoketest | 24600086096644113172124045941573290943964165937719018169213062041232261881036 | 327 |
UVM_INFO @ 156.160000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * | 1 test run | |||
| chip_sw_soc_proxy_external_wakeup | 109403281899534619025460861845955288105845217487375584808596113847336561892101 | 325 |
UVM_INFO @ 157.861000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec | 1 test run | |||
| chip_sw_aon_timer_irq | 67689168963027344379907271524556225545130464017646902075236154868422161906299 | 326 |
UVM_INFO @ 504.273000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds | 1 test run | |||
| chip_sw_aon_timer_wdog_bite_reset | 115466570769201650838953432063605540853370306120251987757071858058020238351894 | 327 |
UVM_INFO @ 182.467000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired | 1 test run | |||
| chip_sw_rv_core_ibex_nmi_irq | 876366580228913067084324908517508890163336193638661963901865917947785837839 | 328 |
UVM_INFO @ 269.232000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (cip_base_scoreboard.sv:689) scoreboard [scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted *, but saw *). | 1 test run | |||
| chip_tl_errors | 32185292170137885449798833901767026995025081531302606927095267317786731979786 | 237 |
TL item was: req: (cip_tl_seq_item@31523) { a_addr: 'h1465414 a_data: 'h667c84f3 a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'h77 a_opcode: 'h1 a_user: 'h268f4 d_param: 'h0 d_source: 'h77 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"} .
UVM_INFO @ 117.777000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (cip_base_vseq.sv:664) [chip_rv_dm_lc_disabled_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * | 1 test run | |||
| chip_rv_dm_lc_disabled | 27369023340056887806448754479357556881111507344499696607672780268452472359698 | 217 |
UVM_INFO @ 124.507000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| Error-[CNST-CIF] Constraints inconsistency failure | 1 test run | |||
| chip_padctrl_attributes | 92347488499549554139132776580605234146189230616327930718995521342959377638235 | 287 |
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
|
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * | 1 test run | |||
| chip_sw_dma_abort | 24445007548106781934604886087748716081390145465722989432675251272973532672420 | 331 |
UVM_INFO @ 211.731000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|