Simulation Results: clkmgr

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.76 %
  • code
  • 69.76 %
  • assert
  • 90.08 %
  • func
  • 73.44 %
  • line
  • 82.37 %
  • branch
  • 87.53 %
  • cond
  • 79.45 %
  • toggle
  • 99.43 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.800s 18.127us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.760s 15.999us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.640s 3.745us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.640s 3.238us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.780s 10.387us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.730s 6.618us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.640s 3.745us 0 1 0.00
clkmgr_csr_aliasing 0.780s 10.387us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.740s 18.118us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.100s 43.479us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.760s 15.198us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.800s 18.127us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.800s 14.671us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.730s 11.962us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.800s 14.671us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.650s 8.272us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.890s 12.880us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.460s 115.753us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.460s 115.753us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.760s 15.999us 1 1 100.00
clkmgr_csr_rw 0.640s 3.745us 0 1 0.00
clkmgr_csr_aliasing 0.780s 10.387us 0 1 0.00
clkmgr_same_csr_outstanding 0.950s 38.021us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.760s 15.999us 1 1 100.00
clkmgr_csr_rw 0.640s 3.745us 0 1 0.00
clkmgr_csr_aliasing 0.780s 10.387us 0 1 0.00
clkmgr_same_csr_outstanding 0.950s 38.021us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.270s 296.313us 1 1 100.00
clkmgr_tl_intg_err 0.750s 7.755us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.730s 134.772us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.730s 134.772us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.730s 134.772us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.730s 134.772us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.590s 2.205us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.750s 7.755us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.800s 14.671us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.730s 11.962us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.730s 134.772us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.730s 133.505us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.640s 3.745us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.270s 296.313us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.640s 3.745us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.640s 3.745us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.270s 296.313us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.990s 50.806us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.790s 127.811us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 57202238598584462151494169556332265561327244589447462272899899732971910201017 81
UVM_INFO @ 2204769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 92924809684488951470759368708484605962170273148776077913868078251948858314730 88
UVM_INFO @ 7755066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 72139371022315954899757745443614167636186105961162761160355124419516593924466 81
UVM_INFO @ 10386527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 43933667127916384961619618426884374156097678382732496501951236671712958319467 81
UVM_INFO @ 14670939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 107669173614621556676870676380569389334874302663115165559371231544762994872096 229
UVM_INFO @ 127810824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 89304624451249352089650203017892933598311170400849856764889580245515101816933 84
UVM_INFO @ 11961848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 106295214438263281272969975734103989741199877183037270690403613341633241301447 83
UVM_INFO @ 8272164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_csr_rw 20546256983634220338216997929334463171901725525382528585698431014279518291044 82
UVM_INFO @ 3745380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 43639759079748978886200098697023319013042777205315140719331260942812219132574 82
UVM_INFO @ 6617578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 57443171414432825034586964057113458866830474765504690132282205099114719762511 80
UVM_INFO @ 50805777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 73671671301258349188996557203081606864010323971452557154915879430428543313492 81
UVM_INFO @ 3237538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 94188708735427893404279995847633685371605989714169017988388920706843842899057 81
UVM_INFO @ 38020896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---