Simulation Results: csrng

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 77.16 %
  • code
  • 90.32 %
  • assert
  • 93.45 %
  • func
  • 47.71 %
  • block
  • 95.11 %
  • line
  • 95.78 %
  • branch
  • 88.31 %
  • toggle
  • 91.48 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
83.33%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 105.330us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 25.840us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 26.101us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 25.000s 1111.998us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 21.586us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 27.105us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 26.101us 1 1 100.00
csrng_csr_aliasing 2.000s 21.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
alerts 1 1 100.00
csrng_alert 2.000s 55.441us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 99.528us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 99.528us 0 1 0.00
stress_all 0 1 0.00
csrng_stress_all 7.000s 148.527us 0 1 0.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 13.251us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 18.963us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 109.982us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 109.982us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 25.840us 1 1 100.00
csrng_csr_rw 2.000s 26.101us 1 1 100.00
csrng_csr_aliasing 2.000s 21.586us 1 1 100.00
csrng_same_csr_outstanding 3.000s 68.704us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 25.840us 1 1 100.00
csrng_csr_rw 2.000s 26.101us 1 1 100.00
csrng_csr_aliasing 2.000s 21.586us 1 1 100.00
csrng_same_csr_outstanding 3.000s 68.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 53.273us 1 1 100.00
csrng_tl_intg_err 3.000s 54.137us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 44.614us 1 1 100.00
csrng_csr_rw 2.000s 26.101us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 2.000s 55.441us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
csrng_stress_all 7.000s 148.527us 0 1 0.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
csrng_sec_cm 2.000s 53.273us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
csrng_sec_cm 2.000s 53.273us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
csrng_sec_cm 2.000s 53.273us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
csrng_sec_cm 2.000s 53.273us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
csrng_sec_cm 2.000s 53.273us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 2.000s 55.441us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
sec_cm_constants_lc_gated 0 1 0.00
csrng_stress_all 7.000s 148.527us 0 1 0.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 2.000s 55.441us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 54.137us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
csrng_sec_cm 2.000s 53.273us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
csrng_sec_cm 2.000s 53.273us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 213.613us 1 1 100.00
csrng_err 3.000s 25.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.041s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:667) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 64644797718677409242451428557032520163429216386019995172795440341704118836172 109
UVM_INFO @ 99528379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:173) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all 115577905045897946827996334207248668033461291685159726975126730941805955908668 125
UVM_INFO @ 148527320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 85973493801759744197688300663246589058971896561527208183543614345302695086235 None