Simulation Results: edn/edn0

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.92 %
  • code
  • 82.84 %
  • assert
  • 96.24 %
  • func
  • 48.67 %
  • block
  • 93.51 %
  • line
  • 96.59 %
  • branch
  • 85.88 %
  • toggle
  • 70.58 %
  • FSM
  • 78.29 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 56.449us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 85.981us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 14.514us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 7.000s 2199.338us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 67.801us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 76.564us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 14.514us 1 1 100.00
edn_csr_aliasing 2.000s 67.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 29.443us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 29.443us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 29.443us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 23.286us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 88.551us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 75.689us 1 1 100.00
disable 1 2 50.00
edn_disable 2.000s 11.735us 1 1 100.00
edn_disable_auto_req_mode 2.000s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 9.000s 917.956us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 47.531us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 67.539us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 85.651us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 85.651us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 85.981us 1 1 100.00
edn_csr_rw 2.000s 14.514us 1 1 100.00
edn_csr_aliasing 2.000s 67.801us 1 1 100.00
edn_same_csr_outstanding 2.000s 19.903us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 85.981us 1 1 100.00
edn_csr_rw 2.000s 14.514us 1 1 100.00
edn_csr_aliasing 2.000s 67.801us 1 1 100.00
edn_same_csr_outstanding 2.000s 19.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.000s 359.817us 1 1 100.00
edn_tl_intg_err 2.000s 654.876us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 58.473us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 88.551us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 359.817us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 359.817us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 359.817us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 359.817us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 88.551us 1 1 100.00
edn_sec_cm 5.000s 359.817us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 88.551us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 654.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 36.000s 2393.846us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 110977178423617846134938804004204536118578493140372110957824069255119488269216 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---