Simulation Results: edn/edn1

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.66 %
  • code
  • 83.44 %
  • assert
  • 97.14 %
  • func
  • 79.41 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 88.77 %
  • toggle
  • 94.93 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 43.438us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 23.444us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.010s 31.370us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 6.340s 1230.765us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.170s 275.372us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.380s 24.756us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.010s 31.370us 1 1 100.00
edn_csr_aliasing 1.170s 275.372us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.210s 45.926us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.210s 45.926us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.210s 45.926us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.210s 27.162us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.450s 91.669us 1 1 100.00
errs 1 1 100.00
edn_err 0.920s 19.620us 1 1 100.00
disable 2 2 100.00
edn_disable 0.720s 135.132us 1 1 100.00
edn_disable_auto_req_mode 0.850s 99.390us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.640s 285.641us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 12.315us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 16.204us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.800s 704.975us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.800s 704.975us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 23.444us 1 1 100.00
edn_csr_rw 1.010s 31.370us 1 1 100.00
edn_csr_aliasing 1.170s 275.372us 1 1 100.00
edn_same_csr_outstanding 1.100s 26.696us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 23.444us 1 1 100.00
edn_csr_rw 1.010s 31.370us 1 1 100.00
edn_csr_aliasing 1.170s 275.372us 1 1 100.00
edn_same_csr_outstanding 1.100s 26.696us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.230s 1144.416us 1 1 100.00
edn_tl_intg_err 1.190s 174.473us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 89.984us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.450s 91.669us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.230s 1144.416us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.230s 1144.416us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.230s 1144.416us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.230s 1144.416us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.450s 91.669us 1 1 100.00
edn_sec_cm 2.230s 1144.416us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.450s 91.669us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.190s 174.473us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 39.880s 5741.737us 1 1 100.00