Simulation Results: hmac

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.08 %
  • code
  • 95.95 %
  • assert
  • 96.74 %
  • func
  • 29.56 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.000s 368.041us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 101.783us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 218.227us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 15.000s 2054.262us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 7.000s 1071.552us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 118.890us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 218.227us 1 1 100.00
hmac_csr_aliasing 7.000s 1071.552us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 4.000s 240.653us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 38.000s 5177.110us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.000s 870.717us 1 1 100.00
hmac_test_sha384_vectors 404.000s 162142.117us 1 1 100.00
hmac_test_sha512_vectors 24.000s 1232.888us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 332.800us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 454.337us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 355.396us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.000s 1300.761us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 88.000s 10692.450us 1 1 100.00
error 1 1 100.00
hmac_error 9.000s 1922.444us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 94.000s 48174.664us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.000s 368.041us 1 1 100.00
hmac_long_msg 4.000s 240.653us 1 1 100.00
hmac_back_pressure 38.000s 5177.110us 1 1 100.00
hmac_datapath_stress 88.000s 10692.450us 1 1 100.00
hmac_burst_wr 12.000s 1300.761us 1 1 100.00
hmac_stress_all 16.000s 2335.372us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.000s 368.041us 1 1 100.00
hmac_long_msg 4.000s 240.653us 1 1 100.00
hmac_back_pressure 38.000s 5177.110us 1 1 100.00
hmac_datapath_stress 88.000s 10692.450us 1 1 100.00
hmac_wipe_secret 94.000s 48174.664us 1 1 100.00
hmac_test_sha256_vectors 10.000s 870.717us 1 1 100.00
hmac_test_sha384_vectors 404.000s 162142.117us 1 1 100.00
hmac_test_sha512_vectors 24.000s 1232.888us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 332.800us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 454.337us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 355.396us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.000s 368.041us 1 1 100.00
hmac_long_msg 4.000s 240.653us 1 1 100.00
hmac_back_pressure 38.000s 5177.110us 1 1 100.00
hmac_datapath_stress 88.000s 10692.450us 1 1 100.00
hmac_burst_wr 12.000s 1300.761us 1 1 100.00
hmac_error 9.000s 1922.444us 1 1 100.00
hmac_wipe_secret 94.000s 48174.664us 1 1 100.00
hmac_test_sha256_vectors 10.000s 870.717us 1 1 100.00
hmac_test_sha384_vectors 404.000s 162142.117us 1 1 100.00
hmac_test_sha512_vectors 24.000s 1232.888us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 332.800us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 454.337us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 355.396us 1 1 100.00
hmac_stress_all 16.000s 2335.372us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 16.000s 2335.372us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 16.452us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 32.637us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 71.079us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 71.079us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 101.783us 1 1 100.00
hmac_csr_rw 1.000s 218.227us 1 1 100.00
hmac_csr_aliasing 7.000s 1071.552us 1 1 100.00
hmac_same_csr_outstanding 2.000s 349.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 101.783us 1 1 100.00
hmac_csr_rw 1.000s 218.227us 1 1 100.00
hmac_csr_aliasing 7.000s 1071.552us 1 1 100.00
hmac_same_csr_outstanding 2.000s 349.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 102.512us 1 1 100.00
hmac_tl_intg_err 3.000s 369.146us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 369.146us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.000s 368.041us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.000s 416.321us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 51.000s 8919.294us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 78.211us 1 1 100.00