Simulation Results

Simulation Results: i2c

18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.04 %

code
86.67 %

assert
96.41 %

func
81.05 %

block
96.30 %

line
95.73 %

branch
93.39 %

toggle
72.68 %

FSM
84.89 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	23.000s	1218.389us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	22.000s	3702.824us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	54.346us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	25.948us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.000s	475.096us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.000s	299.792us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	196.453us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	25.948us	1	1	100.00
	i2c_csr_aliasing	1.000s	299.792us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	308.272us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	35.000s	10685.172us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	152.000s	6797.971us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	19.042us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3600.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	310.000s	5947.561us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	1467.661us	1	1	100.00
	i2c_host_fifo_fmt_empty	64.000s	1947.964us	1	1	100.00
	i2c_host_fifo_reset_rx	5.000s	1898.877us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	815.000s	6795.166us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	15.000s	1753.480us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	105.826us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	5213.427us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.000s	3467.887us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	11.000s	3646.305us	1	1	100.00
	i2c_target_intr_smoke	3.000s	2609.996us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	688.714us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	445.760us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	16.000s	7621.405us	1	1	100.00
	i2c_target_stress_rd	11.000s	3646.305us	1	1	100.00
	i2c_target_intr_stress_wr	1655.000s	22827.973us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	1222.516us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	160.000s	3232.328us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	2110.851us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	31.000s	10198.796us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	6397.260us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	495.702us	1	1	100.00
host_mode_config_perf				1	2	50.00
	i2c_host_perf	152.000s	6797.971us	1	1	100.00
	i2c_host_perf_precise	3600.000s	0.000us	0	1	0.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	15.000s	1753.480us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	155.263us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	573.849us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	8596.869us	1	1	100.00
	i2c_target_nack_txstretch	4.000s	125.053us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	11.000s	504.966us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	765.395us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	26.966us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	39.398us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	221.420us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	221.420us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	54.346us	1	1	100.00
	i2c_csr_rw	1.000s	25.948us	1	1	100.00
	i2c_csr_aliasing	1.000s	299.792us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	23.421us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	54.346us	1	1	100.00
	i2c_csr_rw	1.000s	25.948us	1	1	100.00
	i2c_csr_aliasing	1.000s	299.792us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	23.421us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	140.741us	1	1	100.00
	i2c_sec_cm	2.000s	141.898us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	140.741us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	17.000s	4491.625us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	273.935us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	8.000s	1139.675us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_fifo_watermark	66701154554277789103441534331824901984245190274983232225201890774203038009636	None
	i2c_host_perf_precise	77324141466064860191525877617692684738426174036371370720080235335872717136530	None
	i2c_target_stress_all	51250593022935903224006940208010184531356878798820133255107861428022336706634	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	68401251967137764078906186247182971532632194931169380509466570270032736549701	97	UVM_INFO @ 308272123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	39131044714470369178174355357465625596898867298502988332826716722272886615070	117	UVM_INFO @ 10685172330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	56161845632438113480771937836611761033667596699745569086525166285135123595236	100	UVM_INFO @ 4491624602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	115103677432205310034859201501339566455699348104534584650082015626587228199235	94	UVM_INFO @ 1139674859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	42953425741855515490377242474649530567712118417057675224825257217679941127439	93	UVM_INFO @ 5213426831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	85439048935220240710956125548476036401107431767520207083425324428565533141203	87	UVM_INFO @ 273934515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	36071050488398241060956085579190905439083198180950959194152448882422310923346	88	UVM_INFO @ 10198795576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	33968811738971857199577255825641436841284566764629270470702281462737837171326	94	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @17251