Simulation Results

Simulation Results: keymgr_dpe/darjeeling

18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
65.97 %

code
83.58 %

assert
96.95 %

func
17.37 %

block
97.89 %

line
98.64 %

branch
93.15 %

toggle
61.00 %

FSM
81.54 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%

V1

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	keymgr_dpe_smoke	12.000s	1234.942us	1	1	100.00
csr_hw_reset				1	1	100.00
	keymgr_dpe_csr_hw_reset	1.000s	23.411us	1	1	100.00
csr_rw				1	1	100.00
	keymgr_dpe_csr_rw	2.000s	15.095us	1	1	100.00
csr_bit_bash				1	1	100.00
	keymgr_dpe_csr_bit_bash	4.000s	1371.535us	1	1	100.00
csr_aliasing				1	1	100.00
	keymgr_dpe_csr_aliasing	4.000s	345.295us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	keymgr_dpe_csr_mem_rw_with_rand_reset	2.000s	354.761us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	keymgr_dpe_csr_rw	2.000s	15.095us	1	1	100.00
	keymgr_dpe_csr_aliasing	4.000s	345.295us	1	1	100.00

V2

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
intr_test				1	1	100.00
	keymgr_dpe_intr_test	2.000s	18.525us	1	1	100.00
alert_test				1	1	100.00
	keymgr_dpe_alert_test	2.000s	23.148us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	keymgr_dpe_tl_errors	3.000s	118.729us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	keymgr_dpe_tl_errors	3.000s	118.729us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	1.000s	23.411us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	15.095us	1	1	100.00
	keymgr_dpe_csr_aliasing	4.000s	345.295us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	3.000s	581.382us	1	1	100.00
tl_d_partial_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	1.000s	23.411us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	15.095us	1	1	100.00
	keymgr_dpe_csr_aliasing	4.000s	345.295us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	3.000s	581.382us	1	1	100.00

V2S

4/4 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	keymgr_dpe_sec_cm	8.000s	2941.076us	1	1	100.00
	keymgr_dpe_tl_intg_err	2.000s	62.292us	1	1	100.00
shadow_reg_update_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	530.145us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	530.145us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	530.145us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	530.145us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	keymgr_dpe_shadow_reg_errors_with_csr_rw	3.000s	130.839us	1	1	100.00
prim_count_check				1	1	100.00
	keymgr_dpe_sec_cm	8.000s	2941.076us	1	1	100.00
prim_fsm_check				1	1	100.00
	keymgr_dpe_sec_cm	8.000s	2941.076us	1	1	100.00