Simulation Results: kmac/masked

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.63 %
  • code
  • 65.58 %
  • assert
  • 93.81 %
  • func
  • 79.49 %
  • line
  • 96.85 %
  • branch
  • 89.36 %
  • cond
  • 83.83 %
  • toggle
  • 23.06 %
  • FSM
  • 34.81 %
Validation stages
V1
100.00%
V2
68.97%
V2S
62.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 59.240s 33378.147us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.010s 62.013us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.070s 79.621us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 17.320s 3028.081us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 2.890s 144.456us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.920s 85.208us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.070s 79.621us 1 1 100.00
kmac_csr_aliasing 2.890s 144.456us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.800s 37.873us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.260s 112.487us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 3952.390s 275556.061us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 663.210s 23197.980us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 2646.480s 491873.196us 1 1 100.00
kmac_test_vectors_sha3_256 1636.340s 25421.601us 1 1 100.00
kmac_test_vectors_sha3_384 1611.590s 798848.450us 1 1 100.00
kmac_test_vectors_sha3_512 13.940s 1265.749us 1 1 100.00
kmac_test_vectors_shake_128 2961.260s 157144.031us 1 1 100.00
kmac_test_vectors_shake_256 288.440s 25399.248us 1 1 100.00
kmac_test_vectors_kmac 2.460s 89.960us 1 1 100.00
kmac_test_vectors_kmac_xof 2.520s 217.018us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 279.490s 19711.810us 1 1 100.00
app 0 1 0.00
kmac_app 3.590s 53.330us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 0.750s 1.926us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 1.030s 6.659us 0 1 0.00
error 0 1 0.00
kmac_error 31.220s 7865.442us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.120s 11.386us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.310s 39.252us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 14.900s 1103.273us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.890s 24.168us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 0.890s 103.809us 0 1 0.00
lc_escalation 0 1 0.00
kmac_lc_escalation 1.450s 71.681us 0 1 0.00
stress_all 0 1 0.00
kmac_stress_all 361.960s 6951.250us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.710s 23.881us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.790s 32.501us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.040s 164.093us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.040s 164.093us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.010s 62.013us 1 1 100.00
kmac_csr_rw 1.070s 79.621us 1 1 100.00
kmac_csr_aliasing 2.890s 144.456us 1 1 100.00
kmac_same_csr_outstanding 1.490s 64.095us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.010s 62.013us 1 1 100.00
kmac_csr_rw 1.070s 79.621us 1 1 100.00
kmac_csr_aliasing 2.890s 144.456us 1 1 100.00
kmac_same_csr_outstanding 1.490s 64.095us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 2.250s 118.558us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 2.250s 118.558us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 2.250s 118.558us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 2.250s 118.558us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.100s 1135.546us 1 1 100.00
tl_intg_err 1 2 50.00
kmac_sec_cm 1.280s 25.302us 0 1 0.00
kmac_tl_intg_err 2.830s 491.331us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.830s 491.331us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
kmac_lc_escalation 1.450s 71.681us 0 1 0.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 59.240s 33378.147us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 279.490s 19711.810us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 2.250s 118.558us 1 1 100.00
sec_cm_fsm_sparse 0 1 0.00
kmac_sec_cm 1.280s 25.302us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
kmac_sec_cm 1.280s 25.302us 0 1 0.00
sec_cm_packer_ctr_redun 0 1 0.00
kmac_sec_cm 1.280s 25.302us 0 1 0.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 59.240s 33378.147us 1 1 100.00
sec_cm_fsm_global_esc 0 1 0.00
kmac_lc_escalation 1.450s 71.681us 0 1 0.00
sec_cm_fsm_local_esc 0 1 0.00
kmac_sec_cm 1.280s 25.302us 0 1 0.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 24.920s 2479.158us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 59.240s 33378.147us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 31.820s 1535.213us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 5 test runs
kmac_sideload_invalid 32188880661318177053683979773429494322823797815987861561820117543800162052130 76
UVM_INFO @ 39251571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app 22367113755482251172472599238651024030853537046669132474024420223476085406513 78
UVM_INFO @ 53329754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 72830888424915528851795955620538316735762771242883874386729161722593736004326 77
UVM_INFO @ 6659380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 83928269386789453046215885863530955420244095673652104457721769697912346387381 91
UVM_INFO @ 7865441701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 24837409896404102040465095489194559460535963555201865232737509204199663026607 179
UVM_INFO @ 1535212786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_scoreboard.sv:524) scoreboard [scoreboard] Saw request be handled for app * when that app was not selected. 3 test runs
kmac_app_with_partial_data 7846924061562410456969975548133142318799422792870514151955501288662937961362 77
UVM_INFO @ 1926464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 77304372451509146171491312112663663823137049166678212886604386505122363979554 77
UVM_INFO @ 11385989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 48245772446454776308678942257791640328430511248153347501434094113471777415327 274
UVM_INFO @ 6951250428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). 2 test runs
kmac_lc_escalation 39941559057433797601717933926705988153600407914398830553877594257680019883838 81
UVM_INFO @ 71680757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sec_cm 114623790761063021726323245048217224513153475947906805826451211300079807238935 79
UVM_INFO @ 25302369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_scoreboard.sv:601) scoreboard [scoreboard] Unexpected m_error value in the app response (*) 1 test run
kmac_mubi 38536250854078843044826443756731541543691749224851845782152566963608341084131 89
UVM_INFO @ 2479157569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 1 test run
kmac_entropy_ready_error 8703266847807909039744792957325388491213781029822633022044298897800246580809 78
UVM_ERROR @ 103808651 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 103808651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---