Simulation Results: lc_ctrl/volatile_unlock_disabled

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.59 %
  • code
  • 89.05 %
  • assert
  • 95.97 %
  • func
  • 77.74 %
  • block
  • 95.94 %
  • line
  • 96.87 %
  • branch
  • 89.66 %
  • toggle
  • 79.18 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 73.662us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 31.102us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 88.555us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 92.885us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 150.032us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 112.745us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 88.555us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 150.032us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 238.922us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 38.456us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3601.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 854.911us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 7.000s 753.786us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.000s 292.070us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 4.000s 402.050us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 5105.459us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 220.715us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 66.620us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.000s 2415.817us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 484.860us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 74.539us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 127.701us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 238.030us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.000s 4482.763us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 45.018us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.253s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 13.913us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 54.100us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 54.100us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 31.102us 1 1 100.00
lc_ctrl_csr_rw 1.000s 88.555us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 150.032us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 102.939us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 31.102us 1 1 100.00
lc_ctrl_csr_rw 1.000s 88.555us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 150.032us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 102.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 1178.550us 1 1 100.00
lc_ctrl_tl_intg_err 1.000s 134.090us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.000s 134.090us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 238.922us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1178.550us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1178.550us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1178.550us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1178.550us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1178.550us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1178.550us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1178.550us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1178.550us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 854.911us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 2.000s 292.070us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 489.356us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 275.789us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 275.789us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 7.000s 4153.282us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 9 test runs
lc_ctrl_state_failure 57899494370537475003564242280491090449269028480635749313918710224633271282215 None
lc_ctrl_state_post_trans 47160614197686313943861378366291013805083246409841239516471169732074927749872 None
lc_ctrl_prog_failure 65980231054836887436339124358081166406490308298574049652622904460578488460019 None
lc_ctrl_errors 6535119635914085580430367125734186813381808663362133797470145184889973451570 None
lc_ctrl_jtag_state_failure 110111376863234931040429365207622540652177157835909151186650567966493210322215 None
lc_ctrl_jtag_prog_failure 42119348379842999030689513222088811515673611283154608914632295406789009362734 None
lc_ctrl_jtag_errors 28454030116322456398619223660874334328239630054128940652774904608458004599144 None
lc_ctrl_sec_mubi 93358647262174222521859605310227740672028163103694529279433543263264847475550 None
lc_ctrl_stress_all 60422686256336410097411071916915527628674244107606061454302052944209633317536 None
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_post_trans 33085774678065468159265355950802130859170967040684415987352459450925601449444 177
UVM_INFO @ 292069797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 51055774666530675047968551674110882903989847678435054210902355924592523352701 179
UVM_INFO @ 4153281822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---