Simulation Results: lc_ctrl/volatile_unlock_enabled

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.56 %
  • code
  • 90.94 %
  • assert
  • 96.69 %
  • func
  • 78.06 %
  • block
  • 96.25 %
  • line
  • 97.12 %
  • branch
  • 90.50 %
  • toggle
  • 83.27 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 231.956us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 54.374us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 27.277us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 68.775us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.051us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 40.740us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 27.277us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 1390.912us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 22.532us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 3.000s 985.012us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 3.000s 358.883us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 3.000s 1375.387us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 4974.805us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 148.293us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 166.367us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 2253.412us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 1246.784us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 57.096us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 131.260us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 60.889us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 986.825us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.671us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 84.173us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 1084.256us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 1084.256us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 54.374us 1 1 100.00
lc_ctrl_csr_rw 1.000s 27.277us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.051us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 323.189us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 54.374us 1 1 100.00
lc_ctrl_csr_rw 1.000s 27.277us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.051us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 323.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 238.136us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 377.725us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 377.725us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 1390.912us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 238.136us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 238.136us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 238.136us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 238.136us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 238.136us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 238.136us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 238.136us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 238.136us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.000s 985.012us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 898.720us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 166.317us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 166.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 10039348760797255975043187102042839919926623041214187298123402029337963120793 None
lc_ctrl_state_post_trans 64523217094649828755226612443323511244510760046153003026269322769270248588531 None
lc_ctrl_prog_failure 54920570861260711065703063079531111191938566844199724817447902656581040091154 None
lc_ctrl_errors 74317575170330457006659318718389611342779310542485352276155497111251615111884 None
lc_ctrl_jtag_state_failure 64688998798741239483468179920488349678757453316496837062558345881401493832969 None
lc_ctrl_jtag_state_post_trans 85627180783223177263489520062519454730344563033294578931915862218663257869958 None
lc_ctrl_jtag_prog_failure 111209907630799911053162347270540064502986944772408360616076494965094553757730 None
lc_ctrl_jtag_errors 58611193382512172377041024516393966776661489525761562319357594292718765995087 None
lc_ctrl_sec_mubi 59138682591398571274471177859223389201063843919787433630999605022074384097094 None
lc_ctrl_stress_all 81527806507209308872682477406564370922471357612233985365523921624794030708718 None
lc_ctrl_stress_all_with_rand_reset 2634100947627933636647807194662656643467276478380239413409398906452188272879 None