Simulation Results: otbn

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.17 %
  • code
  • 86.16 %
  • assert
  • 89.90 %
  • func
  • 97.46 %
  • block
  • 99.26 %
  • line
  • 99.46 %
  • branch
  • 94.66 %
  • toggle
  • 84.31 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 9.000s 45.443us 1 1 100.00
otbn_smoke_vectorized 7.000s 135.128us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 46.598us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 60.638us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 16.293us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 48.215us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 6.000s 25.401us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 245.326us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 16.293us 1 1 100.00
otbn_csr_aliasing 6.000s 25.401us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 112.000s 8282.832us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 21.000s 1258.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 30.000s 174.457us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 47.000s 168.473us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 81.000s 838.724us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 82.000s 271.734us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 14.817us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 56.734us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 12.000s 56.877us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 26.792us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 22.921us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 70.018us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 70.018us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 60.638us 1 1 100.00
otbn_csr_rw 4.000s 16.293us 1 1 100.00
otbn_csr_aliasing 6.000s 25.401us 1 1 100.00
otbn_same_csr_outstanding 5.000s 55.777us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 60.638us 1 1 100.00
otbn_csr_rw 4.000s 16.293us 1 1 100.00
otbn_csr_aliasing 6.000s 25.401us 1 1 100.00
otbn_same_csr_outstanding 5.000s 55.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 85.101us 1 1 100.00
otbn_dmem_err 10.000s 71.493us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 6.000s 26.518us 0 1 0.00
otbn_controller_ispr_rdata_err 6.000s 12.526us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 60.190us 1 1 100.00
otbn_urnd_err 4.000s 44.555us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 24.766us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 63.945us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 14.537us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
otbn_tl_intg_err 9.000s 75.183us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 64.000s 264.111us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 45.443us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 10.000s 71.493us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 85.101us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 75.183us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 14.817us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 85.101us 1 1 100.00
otbn_dmem_err 10.000s 71.493us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 56.734us 1 1 100.00
otbn_illegal_mem_acc 8.000s 24.766us 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 46.598us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 85.101us 1 1 100.00
otbn_dmem_err 10.000s 71.493us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 56.734us 1 1 100.00
otbn_illegal_mem_acc 8.000s 24.766us 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 14.817us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 85.101us 1 1 100.00
otbn_dmem_err 10.000s 71.493us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 56.734us 1 1 100.00
otbn_illegal_mem_acc 8.000s 24.766us 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 46.598us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 22.554us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 23.790us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 67.000s 381.059us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 67.000s 381.059us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 30.533us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 320.499us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 15.000s 158.076us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 15.000s 158.076us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 39.531us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 46.598us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 46.598us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 46.598us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 81.000s 838.724us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 46.598us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 46.598us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 160.732us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 46.598us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 321.000s 6614.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 5.461s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_alu_bignum_mod_err 4423551590475818832486567342843909683307674631856616211895077717518865158581 119
UVM_INFO @ 26518240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_stress_all_with_rand_reset 62821024659741809401301628070830248696379297083781860399677881462543096013107 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1