Simulation Results: otp_ctrl

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.94 %
  • code
  • 71.25 %
  • assert
  • 91.39 %
  • func
  • 50.17 %
  • line
  • 87.21 %
  • branch
  • 82.51 %
  • cond
  • 85.09 %
  • toggle
  • 64.70 %
  • FSM
  • 36.74 %
Validation stages
V1
88.89%
V2
65.00%
V2S
44.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.510s 209.732us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.900s 440.041us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.520s 1285.559us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.070s 858.395us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.930s 647.023us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 8.410s 1522.837us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.330s 134.850us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.070s 858.395us 1 1 100.00
otp_ctrl_csr_aliasing 8.410s 1522.837us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.690s 614.224us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.670s 45.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 101.390s 2873.924us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.160s 178.198us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 4.360s 1615.180us 0 1 0.00
otp_ctrl_check_fail 6.810s 1184.055us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 5.310s 281.968us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 13.650s 1199.376us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 6.960s 280.492us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 3.500s 345.909us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 34.090s 4165.233us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.880s 90.583us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 8.430s 857.838us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 7.790s 1140.941us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.190s 642.124us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.410s 63.149us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.760s 334.851us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.760s 334.851us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.520s 1285.559us 1 1 100.00
otp_ctrl_csr_rw 2.070s 858.395us 1 1 100.00
otp_ctrl_csr_aliasing 8.410s 1522.837us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.820s 895.484us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.520s 1285.559us 1 1 100.00
otp_ctrl_csr_rw 2.070s 858.395us 1 1 100.00
otp_ctrl_csr_aliasing 8.410s 1522.837us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.820s 895.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
otp_ctrl_tl_intg_err 15.950s 2875.058us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 15.950s 2875.058us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.900s 440.041us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.900s 440.041us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
otp_ctrl_macro_errs 2.880s 90.583us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
otp_ctrl_macro_errs 2.880s 90.583us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.420s 799.136us 1 1 100.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.160s 178.198us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 6.810s 1184.055us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 13.650s 1199.376us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 13.650s 1199.376us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 13.650s 1199.376us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 13.650s 1199.376us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 13.650s 1199.376us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.900s 440.041us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 13.650s 1199.376us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.900s 440.041us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 242.320s 200000.000us 0 1 0.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 5.310s 281.968us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.900s 440.041us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.900s 440.041us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.880s 90.583us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 65.230s 26275.463us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 24.840s 7582.075us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_partition_walk 54938958603445443657786683854887259659066048385288891843926192990841621427996 160061
UVM_INFO @ 2873923503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 21558373483032640057218321060156302755139089752515309951014689942598687854024 3948
UVM_INFO @ 281967943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_background_chks 80788642023489787884392606361583254288966495038430584465463160094536101944669 814
UVM_INFO @ 1615180411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 37360967593064010052574768585478306975402614981367452494947034393858878617291 4000
UVM_INFO @ 1184054923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2202) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 2 test runs
otp_ctrl_stress_all_with_rand_reset 62248417306516755524121415890221041846235141901671146455937161434793337081056 168
UVM_INFO @ 7582074937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 8883197976535328513338623743168419669089445558881228457506373670206169208046 103
UVM_INFO @ 134850447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 90699525385369515456918342992834653731003845008085065009835043677264128833117 95
UVM_INFO @ 26275462678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_dai_lock 12874646581610522497238831952372407455948919686059524818606334068460829832797 11011
UVM_INFO @ 1199376317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 89790547973620282006236961715277320300676784935166712680132250293356129289984 242
UVM_INFO @ 90582771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all 98264366312430422260509925199021113654951963104001868174624105216012386136737 8021
UVM_INFO @ 1140941369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
otp_ctrl_sec_cm 79715615506496284974617653242456707383915794835847224654668959563790975955936 2443
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---