Simulation Results: rstmgr

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.69 %
  • code
  • 99.25 %
  • assert
  • 98.35 %
  • func
  • 95.48 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.86 %
  • toggle
  • 99.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.720s 74.943us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.620s 91.870us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.980s 35.535us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.490s 136.117us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.300s 43.372us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.830s 96.303us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.980s 35.535us 1 1 100.00
rstmgr_csr_aliasing 1.300s 43.372us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 2.150s 169.390us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.370s 42.645us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.230s 49.857us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.790s 589.583us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.790s 589.583us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.790s 589.583us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.790s 589.583us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 10.880s 1684.569us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.090s 47.259us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.320s 71.858us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.320s 71.858us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.620s 91.870us 1 1 100.00
rstmgr_csr_rw 0.980s 35.535us 1 1 100.00
rstmgr_csr_aliasing 1.300s 43.372us 1 1 100.00
rstmgr_same_csr_outstanding 1.510s 45.569us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.620s 91.870us 1 1 100.00
rstmgr_csr_rw 0.980s 35.535us 1 1 100.00
rstmgr_csr_aliasing 1.300s 43.372us 1 1 100.00
rstmgr_same_csr_outstanding 1.510s 45.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 32.280s 6770.896us 1 1 100.00
rstmgr_tl_intg_err 3.740s 336.739us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 32.280s 6770.896us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 32.280s 6770.896us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.740s 336.739us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.410s 68.613us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.350s 433.967us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.590s 292.586us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 32.280s 6770.896us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.980s 35.535us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.980s 35.535us 1 1 100.00