Simulation Results

Simulation Results: rv_dm/use_dmi_interface

18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.79 %

code
74.48 %

assert
96.66 %

func
92.24 %

block
90.24 %

line
90.14 %

branch
73.55 %

toggle
71.74 %

FSM
62.50 %

Validation stages

V1		92.59%
V2		69.57%
V2S		100.00%
V3		100.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	35.000s	1413.467us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	33.000s	211.608us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	31.000s	215.093us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	41.000s	19726.499us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	33.000s	1086.397us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	36.000s	2740.122us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	32.000s	1619.318us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	34.000s	8309.776us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	185.000s	151662.757us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	34.000s	471.936us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	32.000s	375.465us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	220.771us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	31.000s	124.866us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	34.000s	648.171us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	34.000s	185.900us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	34.000s	235.821us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	38.000s	439.885us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	34.000s	471.936us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	34.000s	273.011us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	33.000s	1166.936us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	220.771us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	33.000s	85.158us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	32.000s	168.113us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	34.000s	133.814us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	75.000s	31529.094us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	46.000s	2202.986us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	37.000s	222.394us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	46.000s	2202.986us	1	1	100.00
	rv_dm_csr_rw	34.000s	133.814us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	32.000s	85.748us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	39.000s	33.490us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	35.000s	1413.467us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	32.000s	231.137us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	32.000s	621.824us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	33.000s	567.017us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	31.000s	610.380us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	37.000s	8995.070us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	33.000s	83.860us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	34.000s	55.624us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	34.000s	3608.966us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	41.000s	278.879us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	34.000s	2182.491us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	33.000s	542.684us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	30.000s	198.612us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	36.000s	8748.237us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	46.000s	1086.311us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	32.000s	144.080us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	6855.000s	10000000.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	35.000s	59.273us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	2335.322us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	2335.322us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	46.000s	2202.986us	1	1	100.00
	rv_dm_csr_hw_reset	32.000s	168.113us	1	1	100.00
	rv_dm_csr_rw	34.000s	133.814us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	431.392us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	46.000s	2202.986us	1	1	100.00
	rv_dm_csr_hw_reset	32.000s	168.113us	1	1	100.00
	rv_dm_csr_rw	34.000s	133.814us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	431.392us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	31.000s	1878.457us	1	1	100.00
	rv_dm_tl_intg_err	39.000s	5397.549us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	39.000s	5397.549us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	34.000s	2182.491us	1	1	100.00
	rv_dm_debug_disabled	31.000s	132.728us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	34.000s	2182.491us	1	1	100.00
	rv_dm_debug_disabled	31.000s	132.728us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	35.000s	1413.467us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	33.000s	240.297us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	57.897us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	57.897us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	33.000s	240.297us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	rv_dm_stress_all_with_rand_reset	35.000s	1028.238us	1	1	100.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	165.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	72521870810087901977162461501468029963236196925617696979438188141855292929775	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23817
	rv_dm_autoincr_sba_tl_access	69836510935024355748509155470131980211941209260853036768846289015170891658769	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10398
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	78349563966251212101480573882278053916144091830077521302017824163791712530658	107	UVM_INFO @ 83859806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	50331459005507401244878572323950542981340674552637812132955983486038660679773	107	UVM_INFO @ 55624018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	104258076718460119870974487098890919319191304649765761031527455008615736566757	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	14818650900877212825156902855061530947657889054646566467371683514402281138101	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	18215164687772267340175965252758425737972109639462694309550171450482828350971	87	UVM_INFO @ 124865507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	778496560591233350856495957066978190323572430148562382507333791680032980327	87	UVM_INFO @ 198611915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	88656527643087107550161651109092809015158802609104972158967616182327235798834	87	UVM_INFO @ 278878797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23865) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	93460490401612233866146069733012802505871508188031369749775089269467563365839	87	). UVM_INFO @ 85157961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---