Simulation Results: rv_timer

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.18 %
  • code
  • 90.45 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 627.407us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 46.988us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 27.783us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 4.000s 900.508us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 17.484us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 67.716us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 27.783us 1 1 100.00
rv_timer_csr_aliasing 1.000s 17.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 7.000s 28981.854us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 1018.412us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 174.000s 603242.622us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 174.000s 603242.622us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.000s 1827.358us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 14.912us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 20.976us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 175.490us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 175.490us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 46.988us 1 1 100.00
rv_timer_csr_rw 1.000s 27.783us 1 1 100.00
rv_timer_csr_aliasing 1.000s 17.484us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 764.065us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 46.988us 1 1 100.00
rv_timer_csr_rw 1.000s 27.783us 1 1 100.00
rv_timer_csr_aliasing 1.000s 17.484us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 764.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 41.839us 1 1 100.00
rv_timer_tl_intg_err 2.000s 327.112us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 327.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 64.867us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 86.176us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 10.000s 1474.593us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 25760167092031383608979504430882309184289270993148573837690502803883404006487 85
UVM_INFO @ 64867112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 43691778734751062695498048391331107355585278520664917514058533697689813265023 84
UVM_INFO @ 86175929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---