Simulation Results: spi_device/1r1w

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.02 %
  • code
  • 89.49 %
  • assert
  • 95.40 %
  • func
  • 70.18 %
  • block
  • 98.40 %
  • line
  • 98.80 %
  • branch
  • 97.11 %
  • toggle
  • 72.46 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 172.000s 33535.635us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 146.552us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 66.665us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 29.000s 779.473us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.000s 1574.733us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 157.256us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 66.665us 1 1 100.00
spi_device_csr_aliasing 14.000s 1574.733us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 11.671us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 36.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 169.597us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 4.817us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 7.275us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 5.000s 1532.220us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 5.000s 1532.220us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 14.000s 924.384us 1 1 100.00
spi_device_tpm_sts_read 2.000s 169.031us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 24.000s 2144.199us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 18.000s 13488.447us 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.000s 5227.496us 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.000s 5227.496us 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 10.000s 1523.758us 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 10.000s 1523.758us 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 10.000s 1523.758us 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 10.000s 1523.758us 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 10.000s 1523.758us 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 11.000s 11919.045us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 10.000s 902.615us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 10.000s 902.615us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 10.000s 902.615us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.000s 139.485us 1 1 100.00
spi_device_read_buffer_direct 17.000s 2376.782us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 10.000s 902.615us 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 72.000s 17329.544us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.000s 144.255us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.000s 144.255us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 252.000s 467671.215us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 172.000s 33535.635us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 87.000s 5740.190us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 462.000s 80682.500us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 32.458us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 59.897us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 86.949us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 86.949us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 146.552us 1 1 100.00
spi_device_csr_rw 2.000s 66.665us 1 1 100.00
spi_device_csr_aliasing 14.000s 1574.733us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 167.721us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 146.552us 1 1 100.00
spi_device_csr_rw 2.000s 66.665us 1 1 100.00
spi_device_csr_aliasing 14.000s 1574.733us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 167.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 79.567us 1 1 100.00
spi_device_tl_intg_err 18.000s 2728.461us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 18.000s 2728.461us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 6638135013761817998464191078938455680722092683841480953389224460242575254608 87
UVM_ERROR @ 3217283 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[903] not found within the scope .
UVM_ERROR @ 3217283 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[903] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 95879657133785094094038810901544204787848263856976771592815371851604511262908 85
UVM_ERROR @ 4763580 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3ba [1110111010] vs 0x0 [0])
UVM_ERROR @ 4826580 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2cf [1011001111] vs 0x0 [0])
UVM_ERROR @ 4904580 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x163 [101100011] vs 0x0 [0])
UVM_ERROR @ 4991580 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2e5 [1011100101] vs 0x0 [0])