Simulation Results: spi_host

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.50 %
  • code
  • 91.30 %
  • assert
  • 94.14 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 48.000s 10472.669us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 18.576us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 51.215us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 1108.182us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 41.342us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 29.987us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 51.215us 1 1 100.00
spi_host_csr_aliasing 1.000s 41.342us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 18.407us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 28.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 41.131us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 113.489us 1 1 100.00
spi_host_error_cmd 1.000s 19.817us 1 1 100.00
spi_host_event 7.000s 770.645us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 28.715us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 28.715us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 28.715us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 178.000s 18925.716us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 168.000s 8723.540us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 107.658us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 28.715us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 28.715us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 48.000s 10472.669us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 48.000s 10472.669us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 244.626us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 896.797us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 45.000s 7330.054us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 124.543us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 113.489us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 45.812us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 17.865us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 191.333us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 191.333us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 18.576us 1 1 100.00
spi_host_csr_rw 1.000s 51.215us 1 1 100.00
spi_host_csr_aliasing 1.000s 41.342us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 218.430us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 18.576us 1 1 100.00
spi_host_csr_rw 1.000s 51.215us 1 1 100.00
spi_host_csr_aliasing 1.000s 41.342us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 218.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 95.736us 1 1 100.00
spi_host_sec_cm 1.000s 150.615us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 95.736us 1 1 100.00