Simulation Results: sram_ctrl/main

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.17 %
  • code
  • 95.09 %
  • assert
  • 97.83 %
  • func
  • 92.60 %
  • block
  • 94.48 %
  • line
  • 95.64 %
  • branch
  • 92.86 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 2731.692us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 209.138us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 94.255us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 132.766us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.650us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 1690.219us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 94.255us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.650us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 196.000s 23625.965us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 104.000s 10281.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 28.000s 32903.944us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 139.000s 9102.869us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 155.000s 30377.365us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 29.000s 13849.463us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 29.000s 23005.570us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 34.000s 15531.925us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.000s 1549.563us 1 1 100.00
sram_ctrl_partial_access_b2b 95.000s 7963.849us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 1335.982us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 2769.474us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 1341.603us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 352.040us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 357.627us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 206.000s 28456.830us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 41.806us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 1821.035us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 1821.035us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 209.138us 1 1 100.00
sram_ctrl_csr_rw 2.000s 94.255us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.650us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 28.893us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 209.138us 1 1 100.00
sram_ctrl_csr_rw 2.000s 94.255us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.650us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 28.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 12725.535us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 2291.750us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 552.222us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 2291.750us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 552.222us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 352.040us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 352.040us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 94.255us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 34.000s 15531.925us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 34.000s 15531.925us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 34.000s 15531.925us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 29.000s 23005.570us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 12725.535us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 2731.692us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 2731.692us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 34.000s 15531.925us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 2291.750us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 29.000s 23005.570us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 2291.750us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2291.750us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 2731.692us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2291.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 16.000s 1081.314us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 45146558265386044696093220759781192394575453243691040188444483563001926690060 None
sram_ctrl_mubi_enc_err 92473828470420412896014993893206381206149817340152405271603618666453583341333 None