Simulation Results: uart

 
18/08/2026 18:34:25 DVSim: v1.50.1 sha: 2c5d921 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.88 %
  • code
  • 92.69 %
  • assert
  • 98.27 %
  • func
  • 90.69 %
  • block
  • 99.00 %
  • line
  • 99.52 %
  • branch
  • 98.16 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 294.290us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 14.737us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 13.703us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 150.468us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 134.221us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 189.587us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 13.703us 1 1 100.00
uart_csr_aliasing 1.000s 134.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 28.000s 22143.060us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 294.290us 1 1 100.00
uart_tx_rx 28.000s 22143.060us 1 1 100.00
parity_error 2 2 100.00
uart_intr 64.000s 102385.740us 1 1 100.00
uart_rx_parity_err 50.000s 34908.276us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 28.000s 22143.060us 1 1 100.00
uart_intr 64.000s 102385.740us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 16.000s 11950.641us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 34.000s 36540.474us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 51.000s 48413.417us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 64.000s 102385.740us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 64.000s 102385.740us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 64.000s 102385.740us 1 1 100.00
perf 1 1 100.00
uart_perf 8.000s 3527.495us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.000s 1643.437us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.000s 1643.437us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.000s 2303.239us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.000s 4021.197us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 9.000s 7159.690us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.000s 3668.707us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 380.000s 144332.196us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 169.000s 170181.908us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 44.855us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 88.620us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 525.532us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 525.532us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 14.737us 1 1 100.00
uart_csr_rw 1.000s 13.703us 1 1 100.00
uart_csr_aliasing 1.000s 134.221us 1 1 100.00
uart_same_csr_outstanding 1.000s 82.321us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 14.737us 1 1 100.00
uart_csr_rw 1.000s 13.703us 1 1 100.00
uart_csr_aliasing 1.000s 134.221us 1 1 100.00
uart_same_csr_outstanding 1.000s 82.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 2.000s 35.023us 1 1 100.00
uart_tl_intg_err 2.000s 397.355us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 397.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 19.000s 2639.070us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 49160910268461636577452351536694086666449522772571909881719604634077792161656 83
UVM_ERROR @ 14838726 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 17238726 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 19638726 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 26518726 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0