Simulation Results: aes/gcm_masked

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.48 %
  • code
  • 95.11 %
  • assert
  • 98.43 %
  • func
  • 65.90 %
  • block
  • 95.67 %
  • line
  • 97.46 %
  • branch
  • 89.46 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 77.301us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 111.391us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 80.469us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 166.351us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 251.867us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 103.605us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 85.616us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 166.351us 1 1 100.00
aes_csr_aliasing 3.000s 103.605us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 111.391us 1 1 100.00
aes_config_error 5.000s 131.137us 1 1 100.00
aes_stress 4.000s 113.840us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 111.391us 1 1 100.00
aes_config_error 5.000s 131.137us 1 1 100.00
aes_stress 4.000s 113.840us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 113.840us 1 1 100.00
aes_b2b 7.000s 103.451us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 113.840us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 111.391us 1 1 100.00
aes_config_error 5.000s 131.137us 1 1 100.00
aes_stress 4.000s 113.840us 1 1 100.00
aes_alert_reset 8.000s 250.401us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 223.808us 1 1 100.00
aes_config_error 5.000s 131.137us 1 1 100.00
aes_alert_reset 8.000s 250.401us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 148.403us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 14.000s 492.683us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 9.000s 214.327us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 8.000s 250.401us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 113.840us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 113.840us 1 1 100.00
aes_sideload 9.000s 92.139us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 8.000s 235.176us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 21.000s 720.634us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 211.802us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 80.765us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 4.000s 230.463us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 4.000s 230.463us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 80.469us 1 1 100.00
aes_csr_rw 2.000s 166.351us 1 1 100.00
aes_csr_aliasing 3.000s 103.605us 1 1 100.00
aes_same_csr_outstanding 3.000s 175.968us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 80.469us 1 1 100.00
aes_csr_rw 2.000s 166.351us 1 1 100.00
aes_csr_aliasing 3.000s 103.605us 1 1 100.00
aes_same_csr_outstanding 3.000s 175.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 4.000s 32.591us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 6.000s 1246.387us 0 1 0.00
aes_control_fi 3.000s 384.718us 1 1 100.00
aes_cipher_fi 3.000s 65.564us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 106.682us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 106.682us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 106.682us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 106.682us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 220.634us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 14.000s 1138.366us 1 1 100.00
aes_tl_intg_err 3.000s 288.299us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 288.299us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 8.000s 250.401us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 106.682us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 106.682us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 111.391us 1 1 100.00
aes_stress 4.000s 113.840us 1 1 100.00
aes_alert_reset 8.000s 250.401us 1 1 100.00
aes_core_fi 4.000s 157.291us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 211.802us 1 1 100.00
aes_config_error 5.000s 131.137us 1 1 100.00
aes_stress 4.000s 113.840us 1 1 100.00
aes_core_fi 4.000s 157.291us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 106.682us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 58.036us 1 1 100.00
aes_stress 4.000s 113.840us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 113.840us 1 1 100.00
aes_sideload 9.000s 92.139us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 58.036us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 58.036us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 58.036us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 58.036us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 58.036us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 113.840us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 113.840us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 6.000s 1246.387us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 6.000s 1246.387us 0 1 0.00
aes_control_fi 3.000s 384.718us 1 1 100.00
aes_cipher_fi 3.000s 65.564us 1 1 100.00
aes_ctr_fi 2.000s 144.315us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 6.000s 1246.387us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 6.000s 1246.387us 0 1 0.00
aes_control_fi 3.000s 384.718us 1 1 100.00
aes_cipher_fi 3.000s 65.564us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 65.564us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 6.000s 1246.387us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 6.000s 1246.387us 0 1 0.00
aes_control_fi 3.000s 384.718us 1 1 100.00
aes_ctr_fi 2.000s 144.315us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 6.000s 1246.387us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 6.000s 1246.387us 0 1 0.00
aes_control_fi 3.000s 384.718us 1 1 100.00
aes_cipher_fi 3.000s 65.564us 1 1 100.00
aes_ctr_fi 2.000s 144.315us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 8.000s 250.401us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 6.000s 1246.387us 0 1 0.00
aes_control_fi 3.000s 384.718us 1 1 100.00
aes_cipher_fi 3.000s 65.564us 1 1 100.00
aes_ctr_fi 2.000s 144.315us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 6.000s 1246.387us 0 1 0.00
aes_control_fi 3.000s 384.718us 1 1 100.00
aes_cipher_fi 3.000s 65.564us 1 1 100.00
aes_ctr_fi 2.000s 144.315us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 6.000s 1246.387us 0 1 0.00
aes_control_fi 3.000s 384.718us 1 1 100.00
aes_ctr_fi 2.000s 144.315us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 4.000s 343.309us 1 1 100.00
aes_fi 6.000s 1246.387us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 6.000s 1246.387us 0 1 0.00
aes_control_fi 3.000s 384.718us 1 1 100.00
aes_cipher_fi 3.000s 65.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 4.085us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 68224471246092263327035388124741525318311905315075303839124493258394784182412 9432
UVM_INFO @ 32591106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 42227226266837213402364244372436996490538263290181134716369554109510158361323 64785
UVM_INFO @ 720634284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 107189720009043008874525138804856735124638940978378498241428464976635177738656 8768
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 7472502204326310392094158942250763717373649280962068731429306117121237763307 112
UVM_INFO @ 4085073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---