Simulation Results: aes/gcm_unmasked

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.27 %
  • code
  • 90.55 %
  • assert
  • 97.75 %
  • func
  • 64.51 %
  • block
  • 90.51 %
  • line
  • 92.69 %
  • branch
  • 82.86 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 90.075us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 66.980us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 79.679us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 114.513us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 161.782us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 214.043us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 72.270us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 114.513us 1 1 100.00
aes_csr_aliasing 3.000s 214.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 66.980us 1 1 100.00
aes_config_error 3.000s 157.828us 1 1 100.00
aes_stress 2.000s 147.380us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 66.980us 1 1 100.00
aes_config_error 3.000s 157.828us 1 1 100.00
aes_stress 2.000s 147.380us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 147.380us 1 1 100.00
aes_b2b 5.000s 262.787us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 147.380us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 66.980us 1 1 100.00
aes_config_error 3.000s 157.828us 1 1 100.00
aes_stress 2.000s 147.380us 1 1 100.00
aes_alert_reset 1669.000s 200000.000us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 52.546us 1 1 100.00
aes_config_error 3.000s 157.828us 1 1 100.00
aes_alert_reset 1669.000s 200000.000us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 86.725us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 143.048us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 1669.000s 200000.000us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 147.380us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 147.380us 1 1 100.00
aes_sideload 3.000s 90.609us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 97.207us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 5.000s 291.786us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 64.879us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 913.904us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 913.904us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 79.679us 1 1 100.00
aes_csr_rw 2.000s 114.513us 1 1 100.00
aes_csr_aliasing 3.000s 214.043us 1 1 100.00
aes_same_csr_outstanding 3.000s 287.939us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 79.679us 1 1 100.00
aes_csr_rw 2.000s 114.513us 1 1 100.00
aes_csr_aliasing 3.000s 214.043us 1 1 100.00
aes_same_csr_outstanding 3.000s 287.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 167.594us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3602.207s 0.000us 0 1 0.00
aes_control_fi 2.000s 53.507us 1 1 100.00
aes_cipher_fi 1.000s 58.698us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 359.458us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 359.458us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 359.458us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 359.458us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 141.272us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 562.265us 1 1 100.00
aes_tl_intg_err 2.000s 194.128us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 194.128us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 1669.000s 200000.000us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 359.458us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 359.458us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 66.980us 1 1 100.00
aes_stress 2.000s 147.380us 1 1 100.00
aes_alert_reset 1669.000s 200000.000us 0 1 0.00
aes_core_fi 2.000s 145.739us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 157.828us 1 1 100.00
aes_stress 2.000s 147.380us 1 1 100.00
aes_core_fi 2.000s 145.739us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 359.458us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 55.982us 1 1 100.00
aes_stress 2.000s 147.380us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 147.380us 1 1 100.00
aes_sideload 3.000s 90.609us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 55.982us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 55.982us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 55.982us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 55.982us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 55.982us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 147.380us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 147.380us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3602.207s 0.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3602.207s 0.000us 0 1 0.00
aes_control_fi 2.000s 53.507us 1 1 100.00
aes_cipher_fi 1.000s 58.698us 1 1 100.00
aes_ctr_fi 2.000s 52.098us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3602.207s 0.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3602.207s 0.000us 0 1 0.00
aes_control_fi 2.000s 53.507us 1 1 100.00
aes_cipher_fi 1.000s 58.698us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 58.698us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3602.207s 0.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3602.207s 0.000us 0 1 0.00
aes_control_fi 2.000s 53.507us 1 1 100.00
aes_ctr_fi 2.000s 52.098us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3602.207s 0.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3602.207s 0.000us 0 1 0.00
aes_control_fi 2.000s 53.507us 1 1 100.00
aes_cipher_fi 1.000s 58.698us 1 1 100.00
aes_ctr_fi 2.000s 52.098us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 1669.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3602.207s 0.000us 0 1 0.00
aes_control_fi 2.000s 53.507us 1 1 100.00
aes_cipher_fi 1.000s 58.698us 1 1 100.00
aes_ctr_fi 2.000s 52.098us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3602.207s 0.000us 0 1 0.00
aes_control_fi 2.000s 53.507us 1 1 100.00
aes_cipher_fi 1.000s 58.698us 1 1 100.00
aes_ctr_fi 2.000s 52.098us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3602.207s 0.000us 0 1 0.00
aes_control_fi 2.000s 53.507us 1 1 100.00
aes_ctr_fi 2.000s 52.098us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3602.207s 0.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3602.207s 0.000us 0 1 0.00
aes_control_fi 2.000s 53.507us 1 1 100.00
aes_cipher_fi 1.000s 58.698us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 17.000s 1588.079us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_alert_reset 50980325852422786966069253434826020284406443717364867357002387563344081211954 15998449
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_fi 62138464865737448820848083882203508647936040383076877993667108685276116503995 None
UVM_FATAL (aes_base_vseq.sv:1082) virtual_sequencer [aes_stress_vseq] 1 test run
aes_stress_all_with_rand_reset 68633405637699537158349655876896320337128145673079244401228042762416253753170 651
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0