Simulation Results: clkmgr

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.73 %
  • code
  • 67.62 %
  • assert
  • 88.02 %
  • func
  • 68.56 %
  • line
  • 81.20 %
  • branch
  • 85.86 %
  • cond
  • 74.81 %
  • toggle
  • 96.23 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
12.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.410s 27.136us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.100s 37.412us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.860s 7.569us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 8.400s 1009.070us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.950s 12.299us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.470s 82.715us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.860s 7.569us 0 1 0.00
clkmgr_csr_aliasing 0.950s 12.299us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.470s 31.678us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.620s 60.013us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.790s 15.737us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.410s 27.136us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.750s 8.608us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.780s 3.405us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.750s 8.608us 0 1 0.00
stress_all 1 1 100.00
clkmgr_stress_all 5.740s 673.243us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.960s 22.728us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 5.800s 182.873us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 5.800s 182.873us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.100s 37.412us 1 1 100.00
clkmgr_csr_rw 0.860s 7.569us 0 1 0.00
clkmgr_csr_aliasing 0.950s 12.299us 0 1 0.00
clkmgr_same_csr_outstanding 1.410s 32.270us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.100s 37.412us 1 1 100.00
clkmgr_csr_rw 0.860s 7.569us 0 1 0.00
clkmgr_csr_aliasing 0.950s 12.299us 0 1 0.00
clkmgr_same_csr_outstanding 1.410s 32.270us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 147.460s 10102.492us 0 1 0.00
clkmgr_tl_intg_err 0.970s 3.703us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 2232.250s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 2232.250s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 2232.250s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 2232.250s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.870s 14.146us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.970s 3.703us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.750s 8.608us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.780s 3.405us 0 1 0.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 2232.250s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.150s 75.365us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.860s 7.569us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 147.460s 10102.492us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.860s 7.569us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.860s 7.569us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 147.460s 10102.492us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.860s 5.733us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.270s 43.910us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 46005411596184314512652850219760397637525573457330981711621231274950409009241 81
UVM_INFO @ 14146089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 21355059756149710124812450263655658867237222050458731932107410921115372187637 88
UVM_INFO @ 3702540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 34569908433143533701861329188417054415241228249517488470973743266373182238412 81
UVM_INFO @ 12299324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 95219999493044340912034478003296909531144399598381345759836158107583808641179 84
UVM_INFO @ 3405229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 27568828936872233244742352187599872026888565014152554152576103432697709366308 85
UVM_INFO @ 43909989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 27254164652516887461840236129051178094253456256237666161595136773477901459165 82
UVM_INFO @ 8608481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 52019465176908852620520725024564039719123414073503450582240009653498325261339 80
UVM_INFO @ 5733178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 59635913570113101379762434196439230103171463382632250522305669629151800733426 82
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1087) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 10692381019181847652860635675886611368338098128368432589228127896258501820146 124
UVM_INFO @ 10102491565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_csr_rw 69815675215467078119742066181778397084567199851335513657317134937337361485075 82
UVM_INFO @ 7568797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 82477701615665447431207165787419678909059955703147029281224803757118784448387 81
UVM_INFO @ 1009069984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 9580529763461271575325413309122695234847213213324120665722288391052246937614 81
UVM_INFO @ 32270071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---