Simulation Results: dma

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.16 %
  • code
  • 90.38 %
  • assert
  • 96.50 %
  • func
  • 59.60 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 7.000s 649.273us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 1972.540us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 7.000s 361.680us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 23.348us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 31.710us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 13.000s 6098.161us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 154.213us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 237.131us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 31.710us 1 1 100.00
dma_csr_aliasing 5.000s 154.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 76.000s 4727.432us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 345.000s 78678.135us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 185.000s 21954.047us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 185.000s 21954.047us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 345.000s 78678.135us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 463.000s 111373.075us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 185.000s 21954.047us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 3.000s 105.603us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 57.000s 7442.057us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 11.252us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 15.485us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 4.000s 88.590us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 4.000s 88.590us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 23.348us 1 1 100.00
dma_csr_rw 2.000s 31.710us 1 1 100.00
dma_csr_aliasing 5.000s 154.213us 1 1 100.00
dma_same_csr_outstanding 3.000s 391.797us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 23.348us 1 1 100.00
dma_csr_rw 2.000s 31.710us 1 1 100.00
dma_csr_aliasing 5.000s 154.213us 1 1 100.00
dma_same_csr_outstanding 3.000s 391.797us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 12.000s 983.839us 1 1 100.00
dma_generic_stress 463.000s 111373.075us 1 1 100.00
dma_handshake_stress 185.000s 21954.047us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 12.000s 2542.058us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 447.867us 1 1 100.00
dma_sec_cm 2.000s 10.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 121.000s 37892.556us 1 1 100.00
dma_longer_transfer 6.000s 1680.426us 1 1 100.00
dma_stress_all_with_rand_reset 19.000s 1424.015us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 106010023659098734031130905439207214656419665543173258456163308906719265767892 112
UVM_INFO @ 1424015165ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---