Simulation Results: edn/edn1

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.10 %
  • code
  • 81.54 %
  • assert
  • 97.14 %
  • func
  • 79.62 %
  • line
  • 97.72 %
  • branch
  • 92.42 %
  • cond
  • 89.85 %
  • toggle
  • 86.78 %
  • FSM
  • 40.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.210s 25.500us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.150s 47.892us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.170s 22.764us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 7.960s 612.023us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.550s 137.995us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.450s 107.236us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.170s 22.764us 1 1 100.00
edn_csr_aliasing 1.550s 137.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.330s 35.048us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.330s 35.048us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.330s 35.048us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.220s 27.568us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.350s 40.349us 1 1 100.00
errs 1 1 100.00
edn_err 1.240s 28.657us 1 1 100.00
disable 2 2 100.00
edn_disable 1.130s 83.674us 1 1 100.00
edn_disable_auto_req_mode 1.270s 54.418us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.560s 179.311us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.170s 52.956us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.250s 117.325us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.870s 25.129us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.870s 25.129us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.150s 47.892us 1 1 100.00
edn_csr_rw 1.170s 22.764us 1 1 100.00
edn_csr_aliasing 1.550s 137.995us 1 1 100.00
edn_same_csr_outstanding 1.260s 14.958us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.150s 47.892us 1 1 100.00
edn_csr_rw 1.170s 22.764us 1 1 100.00
edn_csr_aliasing 1.550s 137.995us 1 1 100.00
edn_same_csr_outstanding 1.260s 14.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.870s 1426.856us 1 1 100.00
edn_tl_intg_err 2.780s 133.113us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.120s 19.137us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.350s 40.349us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.870s 1426.856us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.870s 1426.856us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.870s 1426.856us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.870s 1426.856us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.350s 40.349us 1 1 100.00
edn_sec_cm 5.870s 1426.856us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.350s 40.349us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.780s 133.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 52.470s 9893.469us 1 1 100.00