Simulation Results: hmac

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 69.30 %
  • code
  • 83.11 %
  • assert
  • 95.87 %
  • func
  • 28.92 %
  • block
  • 97.37 %
  • line
  • 98.31 %
  • branch
  • 93.40 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.000s 1720.086us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 186.095us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 60.191us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.000s 600.769us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.000s 201.562us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 70.599us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 60.191us 1 1 100.00
hmac_csr_aliasing 4.000s 201.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 150.000s 44565.436us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 81.000s 6808.186us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 15.000s 968.073us 1 1 100.00
hmac_test_sha384_vectors 34.000s 325.993us 1 1 100.00
hmac_test_sha512_vectors 658.000s 76072.757us 1 1 100.00
hmac_test_hmac256_vectors 19.000s 429.879us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 440.906us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 392.809us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 8.000s 425.242us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 216.000s 5277.026us 1 1 100.00
error 1 1 100.00
hmac_error 89.000s 6921.361us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 40.000s 2711.088us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.000s 1720.086us 1 1 100.00
hmac_long_msg 150.000s 44565.436us 1 1 100.00
hmac_back_pressure 81.000s 6808.186us 1 1 100.00
hmac_datapath_stress 216.000s 5277.026us 1 1 100.00
hmac_burst_wr 8.000s 425.242us 1 1 100.00
hmac_stress_all 86.000s 7031.557us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.000s 1720.086us 1 1 100.00
hmac_long_msg 150.000s 44565.436us 1 1 100.00
hmac_back_pressure 81.000s 6808.186us 1 1 100.00
hmac_datapath_stress 216.000s 5277.026us 1 1 100.00
hmac_wipe_secret 40.000s 2711.088us 1 1 100.00
hmac_test_sha256_vectors 15.000s 968.073us 1 1 100.00
hmac_test_sha384_vectors 34.000s 325.993us 1 1 100.00
hmac_test_sha512_vectors 658.000s 76072.757us 1 1 100.00
hmac_test_hmac256_vectors 19.000s 429.879us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 440.906us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 392.809us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.000s 1720.086us 1 1 100.00
hmac_long_msg 150.000s 44565.436us 1 1 100.00
hmac_back_pressure 81.000s 6808.186us 1 1 100.00
hmac_datapath_stress 216.000s 5277.026us 1 1 100.00
hmac_burst_wr 8.000s 425.242us 1 1 100.00
hmac_error 89.000s 6921.361us 1 1 100.00
hmac_wipe_secret 40.000s 2711.088us 1 1 100.00
hmac_test_sha256_vectors 15.000s 968.073us 1 1 100.00
hmac_test_sha384_vectors 34.000s 325.993us 1 1 100.00
hmac_test_sha512_vectors 658.000s 76072.757us 1 1 100.00
hmac_test_hmac256_vectors 19.000s 429.879us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 440.906us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 392.809us 1 1 100.00
hmac_stress_all 86.000s 7031.557us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 86.000s 7031.557us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 18.109us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 60.332us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 534.469us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 534.469us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 186.095us 1 1 100.00
hmac_csr_rw 1.000s 60.191us 1 1 100.00
hmac_csr_aliasing 4.000s 201.562us 1 1 100.00
hmac_same_csr_outstanding 2.000s 41.004us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 186.095us 1 1 100.00
hmac_csr_rw 1.000s 60.191us 1 1 100.00
hmac_csr_aliasing 4.000s 201.562us 1 1 100.00
hmac_same_csr_outstanding 2.000s 41.004us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 84.938us 1 1 100.00
hmac_tl_intg_err 6.000s 1130.761us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 6.000s 1130.761us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.000s 1720.086us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 125.621us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 15.000s 804.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 29.553us 1 1 100.00