Simulation Results

Simulation Results: i2c

19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.67 %

code
86.46 %

assert
97.67 %

func
81.88 %

block
96.25 %

line
95.68 %

branch
93.29 %

toggle
72.68 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	136.000s	6375.807us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	16.000s	1271.743us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	22.258us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	20.701us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.000s	299.331us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	60.758us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	55.034us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	20.701us	1	1	100.00
	i2c_csr_aliasing	2.000s	60.758us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	70.896us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	31.000s	10492.786us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	355.000s	24657.336us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	29.691us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3600.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	2074.000s	8113.012us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	177.837us	1	1	100.00
	i2c_host_fifo_fmt_empty	41.000s	1757.355us	1	1	100.00
	i2c_host_fifo_reset_rx	7.000s	335.385us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	1038.000s	7504.956us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	21.000s	5835.713us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	4.000s	530.262us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	1637.080us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3601.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	9.000s	817.576us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	54.000s	1312.179us	1	1	100.00
	i2c_target_intr_smoke	11.000s	2300.197us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	194.617us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	513.014us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	54.000s	1312.179us	1	1	100.00
	i2c_target_intr_stress_wr	329.000s	8320.800us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	10.000s	5366.365us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	11.000s	2361.029us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.000s	2952.557us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	5.000s	826.316us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.000s	215.072us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	214.460us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	355.000s	24657.336us	1	1	100.00
	i2c_host_perf_precise	3.000s	101.925us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	21.000s	5835.713us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	13.000s	1018.461us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	450.944us	1	1	100.00
	i2c_target_nack_acqfull_addr	6.000s	787.845us	1	1	100.00
	i2c_target_nack_txstretch	4.000s	818.288us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.000s	2035.338us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	5.000s	1655.063us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	33.190us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	55.210us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	242.865us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	242.865us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	22.258us	1	1	100.00
	i2c_csr_rw	1.000s	20.701us	1	1	100.00
	i2c_csr_aliasing	2.000s	60.758us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	21.190us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	22.258us	1	1	100.00
	i2c_csr_rw	1.000s	20.701us	1	1	100.00
	i2c_csr_aliasing	2.000s	60.758us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	21.190us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	159.190us	1	1	100.00
	i2c_sec_cm	2.000s	103.748us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	159.190us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	23.000s	18014.682us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	246.189us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	25.000s	7499.570us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_fifo_watermark	104259570320861542661511853415857199285892162452568056510441803995649266538809	None
	i2c_target_stress_wr	7150483246376377469446432047411807738029879829063421268342364860501766765649	None
	i2c_target_stress_all	49537951943433315873463472425647675175282760640968502940800241193832757322529	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	113736610599512280045244703558657138746178356369682668860274428014361650135904	97	UVM_INFO @ 70896253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	53042016816938917703419915577284890226238786573412439032917771694212881305667	136	UVM_INFO @ 7499569896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:623) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.fmtfull (addr=, Comparison=CompareOpEq, exp_data=, call_count=289)				1 test run
	i2c_host_stress_all	56004396690594749395346640228840095158012669661815289472514151714979740434301	158	UVM_INFO @ 10492785946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	62715812938012761809547652062275807302829904551874873371550191264703801313464	93	UVM_INFO @ 1637079963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	25211098549768452355930205522904081287623461808301543231280055267449387209928	87	UVM_INFO @ 246188670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	101964197934732489662105039097326763602068358464758208239240670106905263667764	147	UVM_INFO @ 18014682093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---