Simulation Results: lc_ctrl/volatile_unlock_disabled

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.98 %
  • code
  • 89.90 %
  • assert
  • 95.97 %
  • func
  • 78.06 %
  • block
  • 95.85 %
  • line
  • 96.45 %
  • branch
  • 89.43 %
  • toggle
  • 83.25 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.000s 162.829us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 49.999us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 16.287us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 100.717us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 135.135us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 109.018us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 16.287us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 135.135us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 420.120us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 23.417us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 587.506us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 3.000s 598.573us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 9.000s 5551.245us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.000s 1488.230us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 831.983us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 368.638us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 1818.525us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 2972.209us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 115.527us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 1749.260us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 279.421us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 866.057us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 45.039us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.104s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 74.137us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 148.556us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 148.556us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 49.999us 1 1 100.00
lc_ctrl_csr_rw 1.000s 16.287us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 135.135us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 34.027us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 49.999us 1 1 100.00
lc_ctrl_csr_rw 1.000s 16.287us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 135.135us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 34.027us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 1158.362us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 46.929us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 46.929us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 420.120us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1158.362us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1158.362us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1158.362us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1158.362us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1158.362us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1158.362us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1158.362us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1158.362us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 587.506us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3601.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.000s 1883.003us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 334.954us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 334.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 11279633845708486826010275784350594966009911796342321920333554050295951925384 None
lc_ctrl_state_post_trans 40573732493094325746466563989438687593450199233304239647309706071578804626718 None
lc_ctrl_prog_failure 79147555184026465549560244019995899873209810592540468076868119063780751854509 None
lc_ctrl_errors 71282190580607701791164474869461135210382006033753392945523481661432559513457 None
lc_ctrl_jtag_state_failure 90574395507627675859039800245340586837199977849881719029818963086150412228343 None
lc_ctrl_jtag_state_post_trans 69658023422631527187402553906795793150969900312019404836205953847831750291173 None
lc_ctrl_jtag_prog_failure 74976925780824158918150461862154089267439459898146944850720528451409954138360 None
lc_ctrl_jtag_errors 114041728524744606847098956234791053851542422239370550318594409979523308523705 None
lc_ctrl_sec_mubi 43616488140839651734075245598455710191393506452521307921576154224519675586622 None
lc_ctrl_stress_all 84037626736791047580920343071549364062912731022787602501849741056662526113502 None
lc_ctrl_stress_all_with_rand_reset 5487912993816729562410057756349461742418169684289628033820648253880908414917 None