Simulation Results: lc_ctrl/volatile_unlock_enabled

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.54 %
  • code
  • 90.94 %
  • assert
  • 95.97 %
  • func
  • 78.71 %
  • block
  • 96.30 %
  • line
  • 96.97 %
  • branch
  • 90.62 %
  • toggle
  • 83.30 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
V2
73.33%
V2S
70.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 19.442us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 17.219us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 50.478us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 103.346us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.723us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 34.251us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 50.478us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.723us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 319.576us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 1300.092us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 85.839us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 4540.730us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 4.000s 184.871us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 4.000s 412.070us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.000s 10064.381us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 134.656us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 222.177us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 1812.380us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 406.733us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 55.475us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 128.805us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 121.349us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 608.897us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 32.254us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.547s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 60.958us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 26.522us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 26.522us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.219us 1 1 100.00
lc_ctrl_csr_rw 2.000s 50.478us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.723us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 101.439us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.219us 1 1 100.00
lc_ctrl_csr_rw 2.000s 50.478us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.723us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 101.439us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 531.764us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 575.382us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 575.382us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 1300.092us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 531.764us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 531.764us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 531.764us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 531.764us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 531.764us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 531.764us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 531.764us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 531.764us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 4540.730us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.000s 319.576us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 498.939us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 507.930us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 507.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
lc_ctrl_state_failure 60438428335046247168822123116249534865154451553165980922999017678393532191026 None
lc_ctrl_prog_failure 3028785679517026928519501543620185205932376901572653254387849634323221969391 None
lc_ctrl_errors 35054266171328616474291645474978200644452475244857602134677231719394336036251 None
lc_ctrl_jtag_state_failure 2473405148069099313000965538961008670492139144926669098131603842127555310053 None
lc_ctrl_jtag_state_post_trans 69420172782135762633214774986252761888777640565522034740142959703553586852139 None
lc_ctrl_jtag_prog_failure 78574722704956652245723369057755400505830622116664705183385536330228327899 None
lc_ctrl_jtag_errors 36194968028503551487236914843443932113031738085511347196192927933811340930407 None
lc_ctrl_sec_mubi 91646301808833869312113560096763165668208175762425960686001056823885320395234 None
lc_ctrl_stress_all 46462933514991313731347706249161866050566898620341372019877696558799569474192 None
lc_ctrl_stress_all_with_rand_reset 65986967797998903260081538363895055337549246985916317990064208349357559012496 None