Simulation Results: otp_ctrl

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.60 %
  • code
  • 73.51 %
  • assert
  • 94.23 %
  • func
  • 59.05 %
  • line
  • 87.57 %
  • branch
  • 85.01 %
  • cond
  • 87.64 %
  • toggle
  • 70.04 %
  • FSM
  • 37.30 %
Validation stages
V1
100.00%
V2
65.00%
V2S
55.56%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 3.130s 204.850us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 15.840s 3304.266us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 5.330s 1707.842us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.170s 94.814us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.760s 1148.493us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 7.420s 403.294us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.030s 128.265us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.170s 94.814us 1 1 100.00
otp_ctrl_csr_aliasing 7.420s 403.294us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.480s 160.930us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.100s 42.543us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 355.190s 112973.167us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.400s 160.709us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 21.940s 2697.796us 1 1 100.00
otp_ctrl_check_fail 19.720s 986.104us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 5.750s 395.168us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 12.860s 609.461us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 32.090s 8057.012us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 21.360s 793.042us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 27.040s 601.000us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 31.050s 2606.582us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 9.630s 559.442us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 7.570s 244.225us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.250s 170.417us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.500s 134.525us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.850s 114.915us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.850s 114.915us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 5.330s 1707.842us 1 1 100.00
otp_ctrl_csr_rw 2.170s 94.814us 1 1 100.00
otp_ctrl_csr_aliasing 7.420s 403.294us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.800s 1517.155us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 5.330s 1707.842us 1 1 100.00
otp_ctrl_csr_rw 2.170s 94.814us 1 1 100.00
otp_ctrl_csr_aliasing 7.420s 403.294us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.800s 1517.155us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
otp_ctrl_tl_intg_err 35.160s 2993.322us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 35.160s 2993.322us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 15.840s 3304.266us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 15.840s 3304.266us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
otp_ctrl_macro_errs 31.050s 2606.582us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
otp_ctrl_macro_errs 31.050s 2606.582us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.430s 208.827us 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.400s 160.709us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 19.720s 986.104us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 12.860s 609.461us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 12.860s 609.461us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 12.860s 609.461us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 12.860s 609.461us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 12.860s 609.461us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 15.840s 3304.266us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 12.860s 609.461us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 15.840s 3304.266us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 431.690s 40923.255us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 5.750s 395.168us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 15.840s 3304.266us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 15.840s 3304.266us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 31.050s 2606.582us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 98.260s 62620.894us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 100.980s 6825.031us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 2 test runs
otp_ctrl_dai_lock 101709114713826541173471694119718602769115466720726830808164198905622182964267 5564
UVM_INFO @ 609461496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 96442011728324183891738148959109356042452269248560890135388897824754699539534 8848
UVM_INFO @ 244225474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 8037244215468792228133313023018676233536860180635943240684310081990129995710 113065
UVM_INFO @ 112973166589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 63412578830010761421079065557305207911857399328524805349021952799613262999406 95
UVM_INFO @ 62620894385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 79200111346991402223941331883908819776530643008368717463888900562668113723088 11800
UVM_INFO @ 986103665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 1 test run
otp_ctrl_macro_errs 115649144695105003939162609617919261521885415212525276113659110119438168224085 18880
UVM_INFO @ 2606581589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_regwen 79626195371147188604168245555005071576004646445692811629270732534823889485367 3948
UVM_INFO @ 395168169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_test_access 54278786509356613627170071824230263362571335980023068654301311787283600603832 5266
UVM_INFO @ 559442023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---