Simulation Results: rom_ctrl/32kb

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.10 %
  • code
  • 78.36 %
  • assert
  • 97.67 %
  • func
  • 85.27 %
  • block
  • 78.24 %
  • line
  • 78.74 %
  • branch
  • 78.60 %
  • toggle
  • 84.65 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
66.67%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 800.788us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 92.722us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 51.883us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 305.508us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 60.555us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 58.039us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 51.883us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 60.555us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 81.609us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 55.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 293.559us 0 1 0.00
stress_all 0 1 0.00
rom_ctrl_stress_all 10800.000s 0.000us 0 1 0.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 52.148us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 641.415us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 641.415us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 92.722us 1 1 100.00
rom_ctrl_csr_rw 2.000s 51.883us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 60.555us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 66.653us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 92.722us 1 1 100.00
rom_ctrl_csr_rw 2.000s 51.883us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 60.555us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 66.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 5.000s 237.931us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 60.000s 1160.162us 1 1 100.00
rom_ctrl_tl_intg_err 27.000s 382.915us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 60.000s 1160.162us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 60.000s 1160.162us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 60.000s 1160.162us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 60.000s 1160.162us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 800.788us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 800.788us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 800.788us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 27.000s 382.915us 1 1 100.00
sec_cm_bus_local_esc 0 2 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 5.000s 237.931us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 60.000s 1160.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 4 test runs
rom_ctrl_stress_all 64470325426231303515276498512144910864366650326915477375431400393398620346548 None
rom_ctrl_corrupt_sig_fatal_chk 104285087235766169429169488013057083972077196645846439931802255258689611190752 None
rom_ctrl_kmac_err_chk 104278336802597263368046937341955267949487574625399749518156223754357000740649 None
rom_ctrl_stress_all_with_rand_reset 11882609969416708304554837692549146179476086363470549723374759892254151133800 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 14073693985622685575470789736243790552681677792663113211902493637126077098249 88
UVM_INFO @ 293558503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---