Simulation Results: rom_ctrl/64kb

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.21 %
  • code
  • 79.14 %
  • assert
  • 97.23 %
  • func
  • 85.27 %
  • block
  • 77.91 %
  • line
  • 78.48 %
  • branch
  • 77.67 %
  • toggle
  • 84.22 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
77.78%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 1432.326us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 76.161us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 153.290us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 182.022us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 101.492us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 60.877us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 153.290us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 101.492us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 58.120us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 52.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 10.014us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.000s 1108.135us 1 1 100.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 53.539us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 381.823us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 381.823us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 76.161us 1 1 100.00
rom_ctrl_csr_rw 2.000s 153.290us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 101.492us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 364.280us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 76.161us 1 1 100.00
rom_ctrl_csr_rw 2.000s 153.290us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 101.492us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 364.280us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 6.000s 164.558us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 214.000s 2320.564us 1 1 100.00
rom_ctrl_tl_intg_err 29.000s 519.417us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 214.000s 2320.564us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 214.000s 2320.564us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 214.000s 2320.564us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 214.000s 2320.564us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 1432.326us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 1432.326us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 1432.326us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 29.000s 519.417us 1 1 100.00
sec_cm_bus_local_esc 0 2 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 6.000s 164.558us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 214.000s 2320.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 33149688211161095622305861399395259212836056990912254484768934288506753013548 None
rom_ctrl_kmac_err_chk 77481143063080397777268359122647826888222983821563183501706358371810545710690 None
rom_ctrl_stress_all_with_rand_reset 52857215922101767306145379377606433879854358368810632733081077134145600517473 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 45725511767633674995388684533654587565221426701435058018269724715217733208597 88
UVM_INFO @ 10013991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---