Simulation Results: rstmgr

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.06 %
  • code
  • 99.13 %
  • assert
  • 98.35 %
  • func
  • 96.69 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.30 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.690s 60.761us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.460s 62.295us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.280s 38.311us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.900s 62.402us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.830s 40.220us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.710s 96.698us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.280s 38.311us 1 1 100.00
rstmgr_csr_aliasing 1.830s 40.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.930s 136.717us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.510s 38.894us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.430s 59.633us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.810s 652.477us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.810s 652.477us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.810s 652.477us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.810s 652.477us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 21.040s 3197.395us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.310s 42.739us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.360s 59.953us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.360s 59.953us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.460s 62.295us 1 1 100.00
rstmgr_csr_rw 1.280s 38.311us 1 1 100.00
rstmgr_csr_aliasing 1.830s 40.220us 1 1 100.00
rstmgr_same_csr_outstanding 1.720s 66.879us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.460s 62.295us 1 1 100.00
rstmgr_csr_rw 1.280s 38.311us 1 1 100.00
rstmgr_csr_aliasing 1.830s 40.220us 1 1 100.00
rstmgr_same_csr_outstanding 1.720s 66.879us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 26.790s 3421.806us 1 1 100.00
rstmgr_tl_intg_err 4.320s 339.279us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 26.790s 3421.806us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 26.790s 3421.806us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.320s 339.279us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.410s 55.163us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.080s 471.063us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.420s 291.810us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 26.790s 3421.806us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.280s 38.311us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.280s 38.311us 1 1 100.00