Simulation Results

Simulation Results: rv_dm/use_dmi_interface

19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
90.51 %

code
81.71 %

assert
96.74 %

func
93.08 %

block
92.57 %

line
93.41 %

branch
79.82 %

toggle
73.26 %

FSM
80.36 %

Validation stages

V1		92.59%
V2		73.91%
V2S		100.00%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	50.000s	1726.415us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	44.000s	450.030us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	36.000s	173.310us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	66.000s	12630.280us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	48.000s	2280.942us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	67.000s	20428.988us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	55.000s	5058.070us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	66.000s	10662.760us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	72.000s	197040.195us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	45.000s	874.616us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	39.000s	747.361us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	44.000s	314.572us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	35.000s	92.313us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	49.000s	234.494us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	39.000s	1615.755us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	43.000s	76.004us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	51.000s	1319.495us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	45.000s	874.616us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	46.000s	419.773us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	33.000s	274.183us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	44.000s	314.572us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	43.000s	139.359us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	33.000s	102.960us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	39.000s	425.917us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	110.000s	9386.024us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	67.000s	3671.234us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	39.000s	185.686us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	67.000s	3671.234us	1	1	100.00
	rv_dm_csr_rw	39.000s	425.917us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	44.000s	66.369us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	39.000s	28.736us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	50.000s	1726.415us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	42.000s	582.336us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	38.000s	117.391us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	52.000s	519.770us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	51.000s	640.312us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	51.000s	2736.124us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	40.000s	193.096us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	50.000s	2312.786us	0	1	0.00
sba_autoincrement				1	1	100.00
	rv_dm_autoincr_sba_tl_access	66.000s	6818.488us	1	1	100.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	43.000s	303.640us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	50.000s	753.980us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	42.000s	161.155us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	36.000s	86.203us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	55.000s	6574.158us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	56.000s	1450.007us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	48.000s	382.098us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	41.000s	643.837us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	39.000s	66.927us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	45.000s	922.972us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	45.000s	922.972us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	67.000s	3671.234us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	102.960us	1	1	100.00
	rv_dm_csr_rw	39.000s	425.917us	1	1	100.00
	rv_dm_same_csr_outstanding	38.000s	372.597us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	67.000s	3671.234us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	102.960us	1	1	100.00
	rv_dm_csr_rw	39.000s	425.917us	1	1	100.00
	rv_dm_same_csr_outstanding	38.000s	372.597us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	45.000s	1500.187us	1	1	100.00
	rv_dm_tl_intg_err	52.000s	2495.855us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	52.000s	2495.855us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	50.000s	753.980us	1	1	100.00
	rv_dm_debug_disabled	37.000s	35.378us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	50.000s	753.980us	1	1	100.00
	rv_dm_debug_disabled	37.000s	35.378us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	50.000s	1726.415us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	43.000s	107.105us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	43.000s	149.684us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	43.000s	149.684us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	43.000s	107.105us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	58.000s	3219.757us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	276.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	97331341784226745489326153862485500027713086865493680951359217902384573467774	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23877
	rv_dm_bad_sba_tl_access	46982075068259349548203364856646781574613360804817270978221303234656521013155	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23926
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	60068189581444120500489924132477757611851520459114608737438920467156612314810	87	UVM_INFO @ 303640391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	29797356495137111267911016075137715974938972842753966567973481778238866351086	88	UVM_INFO @ 643837303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	30595771214644677275423833758084517840783485159749169647663386400916603495730	107	UVM_INFO @ 193095898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	54665078283650139753582417505069982672304130822678654889252162110445593301925	87	UVM_INFO @ 92312852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	68523270639460842213430593478051891823930077238929950148805953727139296391898	87	UVM_INFO @ 86203278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23864) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	42518385913616328375052366242815812903258716014686757457740251467374187916253	87	). UVM_INFO @ 139358826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	48620489032055242201034035566182554204322521269469930288186159680704266889086	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [rv_dm_common_vseq] Check failed (vseq_done)				1 test run
	rv_dm_stress_all_with_rand_reset	103783315320078339062684143946774879534880848112110481533165403475519274908768	97	UVM_INFO @ 3219756879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---