Simulation Results: rv_timer

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 90.45 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 338.859us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 39.249us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 45.137us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 5.000s 2182.630us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 34.004us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 22.256us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 45.137us 1 1 100.00
rv_timer_csr_aliasing 2.000s 34.004us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 106.075us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 325.310us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 342.000s 544089.748us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 342.000s 544089.748us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 9.000s 223.460us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 20.327us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 13.952us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 56.909us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 56.909us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 39.249us 1 1 100.00
rv_timer_csr_rw 1.000s 45.137us 1 1 100.00
rv_timer_csr_aliasing 2.000s 34.004us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 124.121us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 39.249us 1 1 100.00
rv_timer_csr_rw 1.000s 45.137us 1 1 100.00
rv_timer_csr_aliasing 2.000s 34.004us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 124.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 2.000s 72.034us 1 1 100.00
rv_timer_tl_intg_err 2.000s 176.749us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 176.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 54.247us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 136.254us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 12.000s 13657.310us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 69014103416528724274682104440625431738476299546671065007382961142218114840952 85
UVM_INFO @ 54246789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 29197500620568041430399373045868461093560479410968405968631774486759809137761 84
UVM_INFO @ 136254415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---