Simulation Results: spi_host

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.51 %
  • code
  • 91.01 %
  • assert
  • 95.27 %
  • func
  • 88.24 %
  • block
  • 96.60 %
  • line
  • 98.32 %
  • branch
  • 92.65 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 76.000s 9029.829us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 33.333us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 37.293us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 166.618us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 31.206us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 341.922us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 37.293us 1 1 100.00
spi_host_csr_aliasing 2.000s 31.206us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 36.510us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 97.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 25.026us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 15.000s 1189.952us 1 1 100.00
spi_host_error_cmd 2.000s 27.656us 1 1 100.00
spi_host_event 25.000s 953.425us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 81.410us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 81.410us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 81.410us 1 1 100.00
upper_range_clkdiv 0 1 0.00
spi_host_upper_range_clkdiv 167.000s 200000.000us 0 1 0.00
sw_reset 1 1 100.00
spi_host_sw_reset 6.000s 132.401us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 55.553us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 81.410us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 81.410us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 76.000s 9029.829us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 76.000s 9029.829us 1 1 100.00
stress_all 0 1 0.00
spi_host_stress_all 7.000s 10129.442us 0 1 0.00
spien 1 1 100.00
spi_host_spien 6.000s 1412.877us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 27.000s 963.802us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 60.699us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 15.000s 1189.952us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 46.957us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 22.198us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 74.887us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 74.887us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 33.333us 1 1 100.00
spi_host_csr_rw 1.000s 37.293us 1 1 100.00
spi_host_csr_aliasing 2.000s 31.206us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 55.887us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 33.333us 1 1 100.00
spi_host_csr_rw 1.000s 37.293us 1 1 100.00
spi_host_csr_aliasing 2.000s 31.206us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 55.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 100.860us 1 1 100.00
spi_host_sec_cm 1.000s 76.343us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 100.860us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_upper_range_clkdiv 93376374439025518169732682950406278238246215383687953268870824024605753445128 143
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_stress_all 52224472744600666569731794965390011664511541467664643475176311273310804324714 199
UVM_INFO @ 10129441723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---