Simulation Results: sram_ctrl/main

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.04 %
  • code
  • 93.69 %
  • assert
  • 97.42 %
  • func
  • 94.00 %
  • block
  • 92.66 %
  • line
  • 93.64 %
  • branch
  • 89.29 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.000s 7741.056us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 18.089us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 24.114us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 67.269us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.359us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 354.694us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 24.114us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.359us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 234.000s 5923.651us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 144.000s 52376.193us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 15.000s 1754.941us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 142.000s 3051.788us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 152.000s 12211.001us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 46.000s 13722.667us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 87.000s 83173.204us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 14.000s 1928.395us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 1441.485us 1 1 100.00
sram_ctrl_partial_access_b2b 190.000s 11761.245us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 693.866us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.000s 3513.212us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 692.507us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 922.597us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 689.033us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 284.000s 197783.263us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 47.055us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 75.011us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 75.011us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.089us 1 1 100.00
sram_ctrl_csr_rw 2.000s 24.114us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.359us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 65.948us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.089us 1 1 100.00
sram_ctrl_csr_rw 2.000s 24.114us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.359us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 65.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 3899.741us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1039.134us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1772.634us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1039.134us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1772.634us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 922.597us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 922.597us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 24.114us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 14.000s 1928.395us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 14.000s 1928.395us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 14.000s 1928.395us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 87.000s 83173.204us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 3899.741us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.000s 7741.056us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.000s 7741.056us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 14.000s 1928.395us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1039.134us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 87.000s 83173.204us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1039.134us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1039.134us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.000s 7741.056us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1039.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 9.000s 296.859us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 47809409945973413734255650313863903746676905406895014544651051737895100028487 None
sram_ctrl_mubi_enc_err 33274682827492687117100874206800221591279411451762770029848928335030132562891 None