Simulation Results: uart

 
19/08/2026 21:14:37 DVSim: v1.50.1 sha: e688e72 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.02 %
  • code
  • 92.53 %
  • assert
  • 98.85 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 704.345us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 190.207us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 2.000s 15.326us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 553.894us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 15.030us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 48.994us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 2.000s 15.326us 1 1 100.00
uart_csr_aliasing 1.000s 15.030us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 53.000s 107235.175us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 704.345us 1 1 100.00
uart_tx_rx 53.000s 107235.175us 1 1 100.00
parity_error 2 2 100.00
uart_intr 77.000s 43610.969us 1 1 100.00
uart_rx_parity_err 93.000s 52578.880us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 53.000s 107235.175us 1 1 100.00
uart_intr 77.000s 43610.969us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 47.000s 91231.074us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 16.000s 40132.444us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 83.000s 46756.235us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 77.000s 43610.969us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 77.000s 43610.969us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 77.000s 43610.969us 1 1 100.00
perf 1 1 100.00
uart_perf 169.000s 15021.908us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.000s 5678.924us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.000s 5678.924us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 10.000s 14932.062us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.000s 5378.168us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 5.000s 1068.802us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 8.000s 4392.912us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 424.000s 66881.226us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 1112.000s 461735.012us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 15.846us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 68.281us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 229.380us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 229.380us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 190.207us 1 1 100.00
uart_csr_rw 2.000s 15.326us 1 1 100.00
uart_csr_aliasing 1.000s 15.030us 1 1 100.00
uart_same_csr_outstanding 1.000s 40.820us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 190.207us 1 1 100.00
uart_csr_rw 2.000s 15.326us 1 1 100.00
uart_csr_aliasing 1.000s 15.030us 1 1 100.00
uart_same_csr_outstanding 1.000s 40.820us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 2.000s 39.222us 1 1 100.00
uart_tl_intg_err 2.000s 78.738us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 78.738us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 28.000s 2512.344us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:499) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 7830092714519372734145879398480772382973064153771474383560375231949019074078 86
UVM_ERROR @ 13038046526 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 13038254861 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 221 [0xdd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 13038338195 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 13038588197 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata