Simulation Results: ac_range_check

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.95 %
  • code
  • 93.12 %
  • assert
  • 97.75 %
  • func
  • 57.98 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 35.000s 1952.343us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 38.000s 607.220us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 9.000s 287.996us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 9.000s 23.952us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 49.000s 5250.600us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 30.000s 7639.540us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 9.000s 21.005us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 9.000s 23.952us 1 1 100.00
ac_range_check_csr_aliasing 30.000s 7639.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 10.000s 42.257us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 43.000s 3681.349us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 143.000s 5459.721us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 9.000s 14.791us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 9.000s 23.101us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 63.496us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 63.496us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 9.000s 287.996us 1 1 100.00
ac_range_check_csr_rw 9.000s 23.952us 1 1 100.00
ac_range_check_csr_aliasing 30.000s 7639.540us 1 1 100.00
ac_range_check_same_csr_outstanding 10.000s 321.010us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 9.000s 287.996us 1 1 100.00
ac_range_check_csr_rw 9.000s 23.952us 1 1 100.00
ac_range_check_csr_aliasing 30.000s 7639.540us 1 1 100.00
ac_range_check_same_csr_outstanding 10.000s 321.010us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 6464.971us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 6464.971us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 6464.971us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 6464.971us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 112.000s 9372.629us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 8.000s 12.962us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 119.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 290.000s 2710.604us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 45.000s 1315.124us 1 1 100.00