Simulation Results: aes/gcm_masked

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 85.56 %
  • code
  • 95.55 %
  • assert
  • 98.29 %
  • func
  • 62.84 %
  • block
  • 95.71 %
  • line
  • 97.42 %
  • branch
  • 89.40 %
  • toggle
  • 97.97 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
94.74%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 110.709us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 80.268us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 57.589us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 69.667us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 10.000s 250.221us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 69.921us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 64.029us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 69.667us 1 1 100.00
aes_csr_aliasing 2.000s 69.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 80.268us 1 1 100.00
aes_config_error 3.000s 136.936us 1 1 100.00
aes_stress 3.000s 106.018us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 80.268us 1 1 100.00
aes_config_error 3.000s 136.936us 1 1 100.00
aes_stress 3.000s 106.018us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 106.018us 1 1 100.00
aes_b2b 14.000s 178.713us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 106.018us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 80.268us 1 1 100.00
aes_config_error 3.000s 136.936us 1 1 100.00
aes_stress 3.000s 106.018us 1 1 100.00
aes_alert_reset 3.000s 106.097us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 92.973us 1 1 100.00
aes_config_error 3.000s 136.936us 1 1 100.00
aes_alert_reset 3.000s 106.097us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 234.492us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 10.000s 554.224us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 351.154us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 106.097us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 106.018us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 106.018us 1 1 100.00
aes_sideload 3.000s 83.141us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 7.000s 304.132us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10.000s 382.641us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 5.000s 147.443us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 87.125us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 379.136us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 379.136us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 57.589us 1 1 100.00
aes_csr_rw 2.000s 69.667us 1 1 100.00
aes_csr_aliasing 2.000s 69.921us 1 1 100.00
aes_same_csr_outstanding 2.000s 84.802us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 57.589us 1 1 100.00
aes_csr_rw 2.000s 69.667us 1 1 100.00
aes_csr_aliasing 2.000s 69.921us 1 1 100.00
aes_same_csr_outstanding 2.000s 84.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 709.257us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 7.000s 191.466us 0 1 0.00
aes_control_fi 3.000s 48.705us 1 1 100.00
aes_cipher_fi 2.000s 102.793us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 130.537us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 130.537us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 130.537us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 130.537us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 132.717us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 522.606us 1 1 100.00
aes_tl_intg_err 3.000s 155.890us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 155.890us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 106.097us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 130.537us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 130.537us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 80.268us 1 1 100.00
aes_stress 3.000s 106.018us 1 1 100.00
aes_alert_reset 3.000s 106.097us 1 1 100.00
aes_core_fi 3.000s 106.346us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 5.000s 147.443us 1 1 100.00
aes_config_error 3.000s 136.936us 1 1 100.00
aes_stress 3.000s 106.018us 1 1 100.00
aes_core_fi 3.000s 106.346us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 130.537us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 70.300us 1 1 100.00
aes_stress 3.000s 106.018us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 106.018us 1 1 100.00
aes_sideload 3.000s 83.141us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 70.300us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 70.300us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 70.300us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 70.300us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 70.300us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 106.018us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 106.018us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 7.000s 191.466us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 7.000s 191.466us 0 1 0.00
aes_control_fi 3.000s 48.705us 1 1 100.00
aes_cipher_fi 2.000s 102.793us 1 1 100.00
aes_ctr_fi 3.000s 52.338us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 7.000s 191.466us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 7.000s 191.466us 0 1 0.00
aes_control_fi 3.000s 48.705us 1 1 100.00
aes_cipher_fi 2.000s 102.793us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 102.793us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 7.000s 191.466us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 7.000s 191.466us 0 1 0.00
aes_control_fi 3.000s 48.705us 1 1 100.00
aes_ctr_fi 3.000s 52.338us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 7.000s 191.466us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 7.000s 191.466us 0 1 0.00
aes_control_fi 3.000s 48.705us 1 1 100.00
aes_cipher_fi 2.000s 102.793us 1 1 100.00
aes_ctr_fi 3.000s 52.338us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 106.097us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 7.000s 191.466us 0 1 0.00
aes_control_fi 3.000s 48.705us 1 1 100.00
aes_cipher_fi 2.000s 102.793us 1 1 100.00
aes_ctr_fi 3.000s 52.338us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 7.000s 191.466us 0 1 0.00
aes_control_fi 3.000s 48.705us 1 1 100.00
aes_cipher_fi 2.000s 102.793us 1 1 100.00
aes_ctr_fi 3.000s 52.338us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 7.000s 191.466us 0 1 0.00
aes_control_fi 3.000s 48.705us 1 1 100.00
aes_ctr_fi 3.000s 52.338us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 3.000s 61.349us 1 1 100.00
aes_fi 7.000s 191.466us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 7.000s 191.466us 0 1 0.00
aes_control_fi 3.000s 48.705us 1 1 100.00
aes_cipher_fi 2.000s 102.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 21.000s 1495.565us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 2 test runs
aes_fi 23009227826418298819442171403617479207234054952292045641529921177127626034386 41168
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
aes_stress_all 62425578959692595936134792994079833127706279605647892533341422712717524454540 31955
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 2
----| Seen: 1
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 36978931664831096921119435640322037264628842372845966095149722553861700123009 533
UVM_INFO @ 1495565430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---