Simulation Results: aes/gcm_unmasked

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.12 %
  • code
  • 90.26 %
  • assert
  • 97.75 %
  • func
  • 64.35 %
  • block
  • 90.09 %
  • line
  • 92.29 %
  • branch
  • 82.11 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 71.735us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 80.816us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 55.616us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 127.389us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 1427.709us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 326.611us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 64.911us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 127.389us 1 1 100.00
aes_csr_aliasing 3.000s 326.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 80.816us 1 1 100.00
aes_config_error 3.000s 128.948us 1 1 100.00
aes_stress 3.000s 96.247us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 80.816us 1 1 100.00
aes_config_error 3.000s 128.948us 1 1 100.00
aes_stress 3.000s 96.247us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 96.247us 1 1 100.00
aes_b2b 7.000s 414.802us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 96.247us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 80.816us 1 1 100.00
aes_config_error 3.000s 128.948us 1 1 100.00
aes_stress 3.000s 96.247us 1 1 100.00
aes_alert_reset 2.000s 83.384us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 77.591us 1 1 100.00
aes_config_error 3.000s 128.948us 1 1 100.00
aes_alert_reset 2.000s 83.384us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 256.448us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 546.903us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 83.384us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 96.247us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 96.247us 1 1 100.00
aes_sideload 3.000s 141.343us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 111.952us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 9.000s 473.268us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 72.477us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 174.687us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 174.687us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 55.616us 1 1 100.00
aes_csr_rw 2.000s 127.389us 1 1 100.00
aes_csr_aliasing 3.000s 326.611us 1 1 100.00
aes_same_csr_outstanding 2.000s 76.356us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 55.616us 1 1 100.00
aes_csr_rw 2.000s 127.389us 1 1 100.00
aes_csr_aliasing 3.000s 326.611us 1 1 100.00
aes_same_csr_outstanding 2.000s 76.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 58.054us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 2.000s 74.286us 0 1 0.00
aes_control_fi 2.000s 60.994us 1 1 100.00
aes_cipher_fi 2.000s 60.917us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 141.357us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 141.357us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 141.357us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 141.357us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 595.399us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 934.524us 1 1 100.00
aes_tl_intg_err 2.000s 96.676us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 96.676us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 83.384us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 141.357us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 141.357us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 80.816us 1 1 100.00
aes_stress 3.000s 96.247us 1 1 100.00
aes_alert_reset 2.000s 83.384us 1 1 100.00
aes_core_fi 3.000s 69.079us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 128.948us 1 1 100.00
aes_stress 3.000s 96.247us 1 1 100.00
aes_core_fi 3.000s 69.079us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 141.357us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 65.053us 1 1 100.00
aes_stress 3.000s 96.247us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 96.247us 1 1 100.00
aes_sideload 3.000s 141.343us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 65.053us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 65.053us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 65.053us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 65.053us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 65.053us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 96.247us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 96.247us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 74.286us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 74.286us 0 1 0.00
aes_control_fi 2.000s 60.994us 1 1 100.00
aes_cipher_fi 2.000s 60.917us 1 1 100.00
aes_ctr_fi 3.000s 114.361us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 74.286us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 74.286us 0 1 0.00
aes_control_fi 2.000s 60.994us 1 1 100.00
aes_cipher_fi 2.000s 60.917us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 60.917us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 74.286us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 74.286us 0 1 0.00
aes_control_fi 2.000s 60.994us 1 1 100.00
aes_ctr_fi 3.000s 114.361us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 74.286us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 74.286us 0 1 0.00
aes_control_fi 2.000s 60.994us 1 1 100.00
aes_cipher_fi 2.000s 60.917us 1 1 100.00
aes_ctr_fi 3.000s 114.361us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 83.384us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 74.286us 0 1 0.00
aes_control_fi 2.000s 60.994us 1 1 100.00
aes_cipher_fi 2.000s 60.917us 1 1 100.00
aes_ctr_fi 3.000s 114.361us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 74.286us 0 1 0.00
aes_control_fi 2.000s 60.994us 1 1 100.00
aes_cipher_fi 2.000s 60.917us 1 1 100.00
aes_ctr_fi 3.000s 114.361us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 74.286us 0 1 0.00
aes_control_fi 2.000s 60.994us 1 1 100.00
aes_ctr_fi 3.000s 114.361us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 74.286us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 74.286us 0 1 0.00
aes_control_fi 2.000s 60.994us 1 1 100.00
aes_cipher_fi 2.000s 60.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 27.000s 4094.816us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 23050344692981964159951035313729523428977536112625096276790569429812675548628 2620
UVM_INFO @ 58054408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 97203455977686483847686073025456986963961580891668991800060513836023256840737 934
UVM_INFO @ 4094816280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 68350373314445338693816051185857694799526432830261423154867204148896383498056 5547
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0