Simulation Results: alert_handler

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.57 %
  • code
  • 92.50 %
  • assert
  • 98.11 %
  • func
  • 81.10 %
  • line
  • 99.75 %
  • branch
  • 98.56 %
  • cond
  • 91.92 %
  • toggle
  • 93.23 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 31.320s 373.825us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 8.480s 66.985us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 9.130s 140.032us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 634.460s 10544.235us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 173.620s 2097.120us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 8.910s 102.280us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 9.130s 140.032us 1 1 100.00
alert_handler_csr_aliasing 173.620s 2097.120us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 368.120s 6407.866us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 23.220s 1050.794us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2881.890s 431528.960us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 37.300s 429.649us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 31.320s 373.825us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 20.860s 892.743us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 5.570s 220.324us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 264.200s 60185.070us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1813.190s 79342.569us 1 1 100.00
alert_handler_lpg_stub_clk 966.740s 11887.483us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 3892.430s 168778.439us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 5.870s 686.525us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.430s 65.476us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.590s 27.739us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 21.160s 1194.144us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 21.160s 1194.144us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 8.480s 66.985us 1 1 100.00
alert_handler_csr_rw 9.130s 140.032us 1 1 100.00
alert_handler_csr_aliasing 173.620s 2097.120us 1 1 100.00
alert_handler_same_csr_outstanding 25.070s 208.671us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 8.480s 66.985us 1 1 100.00
alert_handler_csr_rw 9.130s 140.032us 1 1 100.00
alert_handler_csr_aliasing 173.620s 2097.120us 1 1 100.00
alert_handler_same_csr_outstanding 25.070s 208.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 385.570s 10131.861us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 385.570s 10131.861us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 385.570s 10131.861us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 385.570s 10131.861us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1487.690s 91051.016us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 14.210s 898.175us 1 1 100.00
alert_handler_tl_intg_err 3.960s 43.565us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.960s 43.565us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 385.570s 10131.861us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 31.320s 373.825us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 31.320s 373.825us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 31.320s 373.825us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 31.320s 373.825us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 37.300s 429.649us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1813.190s 79342.569us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 37.300s 429.649us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2881.890s 431528.960us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2881.890s 431528.960us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 14.210s 898.175us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 14.210s 898.175us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 14.210s 898.175us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 14.210s 898.175us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 14.210s 898.175us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.210s 898.175us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.210s 898.175us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.210s 898.175us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 14.210s 898.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 13.070s 193.706us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 104364243451091805360650890008261659681900973438886987252668442791011813141534 180
UVM_INFO @ 686524802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 91359561650172311104961184018308698786769131955680566283359892214801734745442 90
UVM_INFO @ 193706013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---