Simulation Results: clkmgr

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.29 %
  • code
  • 68.87 %
  • assert
  • 90.08 %
  • func
  • 69.92 %
  • line
  • 81.71 %
  • branch
  • 86.53 %
  • cond
  • 78.85 %
  • toggle
  • 97.26 %
  • FSM
  • 0.00 %
Validation stages
V1
66.67%
V2
61.54%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 2.480s 190.507us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.070s 34.655us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.400s 40.808us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 7.330s 632.095us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 1.270s 23.851us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.460s 26.721us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 1.400s 40.808us 1 1 100.00
clkmgr_csr_aliasing 1.270s 23.851us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.980s 17.683us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.590s 61.585us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.130s 16.994us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 2.480s 190.507us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 1.140s 18.918us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.980s 7.435us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 1.140s 18.918us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.450s 75.331us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.240s 18.605us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.540s 53.945us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.540s 53.945us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.070s 34.655us 1 1 100.00
clkmgr_csr_rw 1.400s 40.808us 1 1 100.00
clkmgr_csr_aliasing 1.270s 23.851us 0 1 0.00
clkmgr_same_csr_outstanding 0.960s 4.569us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.070s 34.655us 1 1 100.00
clkmgr_csr_rw 1.400s 40.808us 1 1 100.00
clkmgr_csr_aliasing 1.270s 23.851us 0 1 0.00
clkmgr_same_csr_outstanding 0.960s 4.569us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.030s 9.132us 0 1 0.00
clkmgr_tl_intg_err 0.890s 6.791us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.250s 130.287us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.250s 130.287us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.250s 130.287us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.250s 130.287us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.010s 12.195us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.890s 6.791us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 1.140s 18.918us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.980s 7.435us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.250s 130.287us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.950s 45.865us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.400s 40.808us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.030s 9.132us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.400s 40.808us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.400s 40.808us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.030s 9.132us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.880s 11.579us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.330s 60.597us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 56934781254708086961961743861339825070609640088333293126769088436261004038259 81
UVM_INFO @ 12194565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 40693499534273916410317817147552444080129065520120996843239479026733007688575 92
UVM_INFO @ 6790754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 29397724868090393634494054041729481701300229496398219584443452522066756366128 81
UVM_INFO @ 23851009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 23607383997257148365858489417923541132119830772850316844172522491793030109323 82
UVM_INFO @ 18917627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 29332755385172116597347150704412499274110976284330855384344751055560398004573 84
UVM_INFO @ 60596510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 15212032887815503728610440493561288903504594736385911091360858709293758509106 84
UVM_INFO @ 7435358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 1937767065275228582181919056111969145810723216924071556792170898073842057989 83
UVM_INFO @ 75331197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en 1 test run
clkmgr_regwen 87705415260958804219118676045248244473775803317113133181317155820468577584994 80
UVM_INFO @ 11579437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 82328796638693679801940354176711861846271879605659530142076111572005959278519 88
UVM_INFO @ 9132432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 29100916937867005675887872397007770546300149523614433630499398919152744693268 81
UVM_INFO @ 632095265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 96082588985104564956852662401123410633285661729263345713231973224671759341543 81
UVM_INFO @ 4569054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---